( ESNUG 469 Item 9 ) -------------------------------------------- [09/27/07]
From: Jonathan Bahl <jonathan.bahl=user domain=cotconsulting hot mom>
Subject: Jonathan on minimizing your density gradients inside IC Compiler
Hi John,
Here's my trick to improve your design's convergence in IC Compiler for
congested designs by controlling the cell density gradient in the design.
It is based on preserving placement resources for late stage design
modifications. These modifications include clock tree buffering, ECOs, SI
timing fixes, hold buffering or STA driven optimizations.
For example, after placement, a design with an average standard cell density
of 80% could have regions of density 50% or lower but it also most likely
will have regions of 95% and higher. In the regions over 95% it's very
difficult to add cells without perturbing your existing timing, congestion
or SI during legalization. By controlling the gradient, you can reduce the
number cells that are affected in later stages.
I have used this methodology in IC Compiler place_opt in the past. Here
is an example of behavior for an 80% utilized design. The runtimes are
represent only place_opt runtimes.
1. place_opt [baseline runtime]
- This will result in a very smooth density gradient with most
regions >75% and <85%. However, if the design has congestion
issues, it will be unroutable.
2. place_opt -congestion [runtime ~ 1.5X baseline]
- By using the -congestion switch, place_opt will remove as much
congestion as possible, but will also result in pockets of 95-100%
utilization as well as many areas <50%. Convergeance in later
stages will be affected in QoR as well as runtime.
- If a design is heavily congested this may be the best approach.
- For slightly congested designs this method actually damages the
density gradient of a design by over-optimizing congestion.
3. set_congestion_options -max_util 0.87;
place_opt -congestion [runtime <1.5X baseline]
- This will result in a reasonable amount of congestion removal.
- There will be very few regions >90%.
The "set_congestion_options -max_util" switch is a global switch that is
observed locally. The ICC placer will break the design into local grids
and the max_utilization factor is obeyed in each grid. The resulting
density characteristics of your design can be observed by viewing the
cell density map and preserved by dumping out a screenshot.
The usage model I recommend is to get your design through place_opt and
determining the standard cell utilization before determining the user
density control. If a design only has a small amount of congestion, I
then start with a max utilization value that will use 1/3 of the "white
space". (White space is the percentage of the design that is not
utilized. For instance, the design at 80% utilization has 20% white
space.) If I am to use 1/3 of the white space, then I set the max
utilization to "0.8 + 0.2/3 = 0.87".
- Jonathan Bahl
COT Consulting, Inc. Toronto, Canada
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