( ESNUG 469 Item 5 ) -------------------------------------------- [09/27/07]

Subject: ( ESNUG 468 #3 ) DFM, modified LEFs, Calibre, benchmark cheating

> Who cares if the vendor modifies the LEFs?  If you are running a proper
> benchmark, you should run a check DRC in a full GDS-based signoff with a
> tool such as Calibre/Hercules/Mojave/PVS!  This way such an error would
> get revealed.  Plus in the end, these are the tools we all sign off with,
> and if I'm running a benchmark and relying on a vendor's P&R tool to
> report their own errors, this just seems a bit wrong.
>
>     - Jeff Echtenkamp
>       Broadcom Corporation                       Irvine, CA


From: Jonathan Zhang <jonathan.zhang=user domain=atheros hot mom>

Hi, John,

Regarding the "Is it cheating if the LEFs pass the DRC check?" discussion,
I agree with most of the comments.  DRC signoff using a GDS-based tool such
as Calibre is a must as long as the eval is in anyway router related.  If
the user company doing the eval wasn't even doing that, I wonder if they
were really serious about the eval at all.

When we ramp up to a new tech node, we always do modifications to the fab
tech files.  These files, in default, are "safe" rather than optimized.

    - Jon Zhang
      Atheros Communications, Inc.               Santa Clara, CA

         ----    ----    ----    ----    ----    ----   ----

From: Lou Scheffer <lou=user domain=cadence hot mom>

Hi, John,

I find the attitude "if it passes DRC, it's OK" to be very surprising.

The entire DFM industry segment exists because there can be a big difference
in yield between two different designs, each of which meets all the official
design rules.  As an example, why do DFM tools insert redundant vias?  After
all, the design would pass DRC perfectly cleanly without them.  Same applies
to hot spot removal, "recommended" rules, and so on.  Would the design pass
DRC without these?  Yes.  Would it have decent yield?  Probably not...

It's not at all surprising that a foundry LEF would have bigger than minimum
rules in it.  Furthermore these extra spacing rules can be quite tricky; you
don't want to force bigger rules everywhere, but just where they are needed.

A lot of these complex rules are intended to reduce litho hot spots, which
depend in very complicated ways on the surrounding geometry.  Although your
design could pass DRC without these advanced rules, you can be sure they did
not get into the LEF by accident -- it's quite tricky to write them so that
they get rid of various manufacturing problems without affecting density any
more than necessary.  Clearly the foundry believes these additional rules
are needed for good yield; otherwise why go to the trouble of adding them?

I was not involved in any of these evaluations in any way, but I am quite
surprised to see anyone say "DRC clean" == "Decent yield".  This was never
strictly true, and is less and less of a working approximation in every
generation.  The market for DFM tools shows that the VCs with their wallets,
and the existing companies with their R&D budgets, have put their money
behind this observation.

    - Lou Scheffer
      Cadence                                    San Jose, CA
Index    Next->Item








   
 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)