( ESNUG 469 Item 3 ) -------------------------------------------- [09/27/07]
Subject: Jason on Synopsys DC-Topo vs. Cadence RTL Compiler physical stuff
> Synopsys DC-Topo -- power optimization & estimates, CTS, PhysOpt fading,
> congestion and what's coming up in rev 2007.12.
>
> - from http://www.deepchip.com/wiretap/070815.html
From: Jason Ware <jware=user domain=cadence hot mom>
Hi, John,
I watched your DAC interview with Gal Hasson on Synopsys DC-Topo and wanted
to clear up a few misconceptions about Cadence RTL Compiler's physical
solution. Gal compares it to the "old technology" of Synopsys Floorplan
Manager, in fact, nothing could be further from the truth.
Cadence RTL Compiler's physical solution consists of two parts, Physical
Layout Estimation (PLE) and Predict Quality of Silicon (PQOS). PLE has been
in production since version 5.1 (2005) and has over 100 tapeouts with public
endorsements from several customers. In fact, all RTL Compiler users can
use PLE today. The following commands are all that is needed to use PLE.
set_attr lef_library technology.lef
set_attr cap_table_file technology.capTbl
read_def mydesign.def
This will provide prediction within 10% of final post-P&R numbers plus every
aspect of synthesis is physically aware. Our RTL Compiler Global Mapper pre-
analyzes the libraries and physical information and does a TIMING and POWER
aware map and structure with generic gates. This gives a better starting
point for synthesis and optimization as opposed to the "old technology" of a
blind map to generic and hope to clean up later.
Our PQOS is an extension to this technology and works with the PLE opto to
further refine physical prediction. PLE gets you to within 10% of final P&R
timing numbers, with the last 10% is usually caused by long wires (outliers)
that are hard to physically estimate. Our "predict_qos" command uses First
Encounter's silicon virtual prototyping to bring the timing of the placement
-dependent wires back into synthesis. (These are the real source of logical
vs. physical timing differences -- the 10% of wires that are long wires
either between cells, connections to macros or I/O's, or detoured routes.
After synthesis, users can feed the new DEF placement forward for final P&R.
- Jason Ware
Cadence Plano, TX
Index
Next->Item
|
|
