( ESNUG 468 Item 13 ) ------------------------------------------- [09/13/07]
Subject: User reports new hyperscaling in Mentor Calibre nmDRC is awesome
> 6. This year the Mentor Calibre nmDRC marketing folks are gushing
> about how their DRC baby can use multi-termed checks that have up
> to hundreds of terms each -- whereas Cadence/Synopsys/Mojave DRC
> can't. IBM will talking about this at their booth. Also this
> year they can read and write LEF/DEF, Milkway, OpenAccess -- with
> the only holdout being Magma Volcano because Magma won't let them!
> (booth 3676) Ask for Michael White. Freebie: colorful kite
>
> - from http://www.deepchip.com/gadfly/gad060107.html
From: David Guan <guan=user domain=cswitch not calm>
Hi, John,
I wanted to share some results we saw trying out Calibre nmDRC's new
hyperscaling feature. It leverages DRC runtimes without forcing you to buy
additional hardware and doesn't affect existing SVRF decks. It should work
just fine with old and new decks.
We decided to compare DRC fullchip runs using the 2007.2 version (with and
without hyperscaling) on a 3GB GDSII SOC chip we are currently designing in
90 nm.
The ruledeck we used was provided by our foundry; no significant changes
made. I decided to split the deck into 4 parts to optimize resources:
Metal Layer, Base Layer, Antenna, and LatchUp
Overall, we performed 3 runs - regular MT Flex, hyperscaling with split
ruledeck and hyperscaling without split ruledeck.
We used 3 Linux workstations (each having 4 CPUs) and we used 3 Calibre
hdrc licences (Calibre - turbo 8).
Here's what we saw:
Full Rule Deck
Regular MT Flex (hrs) Hyperscaling (hrs) Total
33.5 5.0 6x improvement
Split Rule Deck
Regular MT Flex (hrs) Hyperscaling (hrs)
MetalLayer 34.0 3.5
BaseLayer 20.0 2.8
Antenna 25.5 2.0
LatchUp 6.0 3.5
Total 85.5 11.25 8x improvement
The above info used the latest Calibre release, ixl_cal_2007.2_34.24.
The command line options used for HyperScaling is:
calibre -64 -turbo 8 -hyper -remotefile rbm8
The command line used for MTflex is:
calibre -64 -turbo 8 -remotefile rbm8
Very impressive performance improvement.
8X faster and at no extra cost? This tool rocks!
Of course, if you add more hardware, your results are only going to
improve even more.
- David Guan
Cswitch Corp. Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: John Cooley <jcooley=user domain=zeroskew not calm>
To: David Guan <guan=user domain=cswitch not calm>
Hi, David,
GREAT write-up!
My only questions are what fab did you run this test on? TSMC 90 nm?
Also what size design are you talking about? # of instances, # of nets?
- John Cooley
ESNUG/DeepChip.com Holliston, MA
---- ---- ---- ---- ---- ---- ----
From: David Guan <guan=user domain=cswitch not calm>
To: John Cooley <jcooley=user domain=zeroskew not calm>
Hi, John,
Thank you for your kind word. I just wanted to pass on my excitements.
Our fab of choice is Chartered 90 nm.
On your other questions # of nets on the chip, I do not have a number to
give. This chip has a few pieces of IPs and substatial amount of memory
macros, in addition to the usual place and routed blocks.
- David Guan
Cswitch Corp. Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: John Cooley <jcooley=user domain=zeroskew not calm>
To: David Guan <guan=user domain=cswitch not calm>
Hi, David,
The # of nets and # of instances gives a measure of the complexity of the
chip -- 3 GB GDSII says very little. :( Is there any way you could give
me those two numbers, David? They make a big difference in your report.
- John Cooley
ESNUG/DeepChip.com Holliston, MA
---- ---- ---- ---- ---- ---- ----
From: David Guan <guan=user domain=cswitch not calm>
To: John Cooley <jcooley=user domain=zeroskew not calm>
Hi, John,
Let's what we can do with the number I do have. The chip has a total of
525 million transistors. How do you turn that into the # of instances? By
dividing by 8? That would mean about 65 million gates?
- David Guan
Cswitch Corp. Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: John Cooley <jcooley=user domain=zeroskew not calm>
To: David Guan <guan=user domain=cswitch not calm>
Hi, David,
I'm confused. How can you know the design has 525 million transistors, yet
not know the instance count and the net count? Instance and net counts are
in every P&R report... Huh?
- John Cooley
ESNUG/DeepChip.com Holliston, MA
---- ---- ---- ---- ---- ---- ----
From: David Guan <guan=user domain=cswitch not calm>
To: John Cooley <jcooley=user domain=zeroskew not calm>
Hi, John,
Now I see why I confused you. Our chip is NOT done using a P&R tool. Not
at the full chip level. Only a portion of the chip is done using a P&R
tool. Full chip assembly is done inside a layout editor, ICStation.
The 525 million transistor count is based on Calibre's report.
Hope this clears up any confusion I created for you.
- David Guan
Cswitch Corp. Santa Clara, CA
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