( ESNUG 468 Item 9 ) -------------------------------------------- [09/13/07]
Subject: ( ESNUG 467 #12 ) Mentor 0-in trips up vs. Cadence Conformal CDC
> I was wondering if anyone out there has done a comparison between Atrenta
> Spyglass CDC (Clock Domain Crossing) vs. Cadence's Conformal CDC check,
> and what their thoughts are?
>
> - Paul Min
> SiRF Technology, Inc. San Jose, CA
From: Ben Sum <bens=user domain=ivivity not calm>
Hi, John,
I saw your recent post on CDC and wanted to share my experiences.
I designed more than ten ASICs in my career and each of them had multiple
clock domains. Although designing asynchronous logic can be done in such a
manner that's not rocket science, we definitely need to pay extra attention,
otherwise the chip can be DOA with a minor asynchronous logic bug.
This happened on several designs that I worked on.
Currently, we use Conformal CDC check to locate and fix critical CDC bugs.
I like it's easy to use interface.
We had also used 0-in in the past for CDC checking, but had bad experience
and therefore the switch. 0-in CDC was a pain to setup (definitely not
out-of-the-box) and it had verbose reporting that made it difficult to
distinguish between real and non-real CDC issues -- this resulted in us
missing a CDC bug, and getting a DOA chip back. This was when we turned
to Conformal CDC and had a good experience and using it until now.
To keep things simple, our rule of thumb for CDC logic is to use double
DFFs to synchronize the control path and to use the MUX to synchronize the
data path. However, it is not realistic to verify the asynchronous logic
in the RTL simulation because it doesn't show metastability. With million
gate design nowadays, it is almost impossible to run gate level SDF back-
annotated simulation. Therefore, simulation can not be used to verify our
asynchronous path.
Instead we used Conformal CDC for asynchronous path verification. The tool
is designed to verify the structure of the asynchronous logic and it is very
easy to use, about 10 lines of script to define clock domain and the rule
how to check the structure of the asynchronous logic. The rule is typically
DFFs synchronizer and MUX synchronizer with option such as number of DFF
stage in the synchronizer, combinational logic and number of fanout in the
cross domain path. You can specify multiple rules if needed.
For an 8 million gate ASIC with ~20 clocks, it takes about 1 hour to check
the asynchronous path logic for the entire chip. The tool reports all the
asynchronous paths whether they are PASSED and FAILED the defined rule. If
the path is FAILED, the tool shows how the FAILED logic violates the defined
rule in the schematic. The tool can also detect convergence and divergence
of signal in the cross domain path. It is very important to make sure that
convergence and divergence issue don't create functional bug.
A major $$$ bonus is that Conformal CDC was included with LEC! We found
that out after our getting our DOA-chip back, when getting support on LEC.
This saved us quite a lot of money. A definite plus for management.
- Ben Sum
iVivity, Inc. Norcross, GA
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