( ESNUG 468 Item 8 ) -------------------------------------------- [09/13/07]
Subject: ( ESNUG 467 #12 ) Mentor 0-in kicks ass vs. Atrenta Spyglass CDC
> I was wondering if anyone out there has done a comparison between Atrenta
> Spyglass CDC (Clock Domain Crossing) vs. Cadence's Conformal CDC check,
> and what their thoughts are?
>
> - Paul Min
> SiRF Technology, Inc. San Jose, CA
From: Mike Birenbach <mbirenba=user domain=qualcomm not calm>
Hi, John,
Here are my observations from running a design (glue logic, an interrupt
controller, timers, control/status registers, and clock/reset control for
a CPU) through 0-in and Spyglass CDC checkers.
The versions I used in this comparision: 0-in 2.5d and Spyglass 3.8.3.
0. Simulation Model CDC checks
0-in not only performs static CDC checks, it can also support dynamic CDC
checks in simulation. It can output coverage assertions for every clock
domain crossing and can generate Verilog RTL that will randomly adjust
data at the RX flops of every CDC crossing to simulate different cross
clock domain signal timing. This, of course, relies on functional checks
within the existing testbench to catch any errors.
In addition to adding to the simulation environment, 0-in can also use
the assertions in its formal engine to test the block.
Spyglass does not support any of this. I did not have a chance to try
these features of the Spyglass tool.
1. General Setup
Looking at the setup files required (1 for 0-in vs 4 for Spyglass) and
number of lines of setup info (154 vs 606) 0-in was simpler to set up.
2. Schematic GUI
The 0-in schematic viewer was much better for two reasons.
First, I did not notice a single bug nor seemingly incorrect action while
using it. It just worked. Spyglass did not handle clicks on pins
bringing up additional schematic information correctly. It would
alternately choose to remove what you had been looking at or bring up the
new things and zoom to a new place in the schematic. 0-in handled these
clicks intuitively, bringing up new information and either not zooming at
all or zoom out. 0-in never deleted what was already shown in the
schematic, just added to it.
Second, the schematic shown is based on the source RTL. Spyglass shows
a schematic based on the synthesized result. The Spyglass schematic
therefore is much harder to read as there are intermediary signals
buffers/invertors that are not in the original RTL.
3. Looking at Warnings using their GUIs
There were initially ~350 total warning messages from 0-in, far less than
the ~900 clock_sync01 (one of several message types) Spyglass reported.
Due to the grouping by message type by function (or block) by the 0-in
GUI, it is very easy to see patterns in messages and quickly determine
what to do. Spyglass only groups by message type (at least in the part
of the GUI that lets you use a context sensitive menu to view schematics
and create waivers).
Further refinement of the 0-in setup file brought the total warnings down
to around 200. Same was true for Spyglass clock_sync01 warning; however
Spyglass required runs with multiple settings to get similar conclusions.
4. Defining Custom Synchronizers
Defining custom synchronizers is MUCH simpler in 0-in. Observe the lines
needed to describe our edge detectors:
// 0in set_cdc_synchronizer custom -module edge_detect
// 0in set_cdc_port_domain reset edge_stb -clock clk -module edge_detect
// 0in set_cdc_port_domain async_edge edge_in -async -module edge_detect
// 0in set_cdc_port_domain tcr_async_reset_atpg_ctrl \
tcr_async_set_atpg_ctrl \
tck_sel tck test_obs_pt -ignore -module edge_detect
The Spyglass method of "recognizing" a structure by building a Verilog
model of the synthesized result is not only more complex it is subject to
possible error due to potential changes in the synthesis and/or RTL
source for the edge detect.
0-in recognizes custom synchronizers by name; fewer mistakes are made.
Note the description from 0-in simply describes the name, and then the
synchronous nature of each of the functional pins of the block.
In contrast to the 4 lines of 0-in setup, Spyglass files describing edge
detects required 3 files and 85 lines of text.
5. Black Box I/Os
Defining black box I/O for completely asynchronous BIG_CPU_top sub-module
is simpler in 0-in. In Spyglass this required ~100 lines of text. For
0-in it was just 3:
// 0in set_black_box BIG_CPU_top=20
// 0in set_cdc_port_domain -input * -async -module BIG_CPU_top
// 0in set_cdc_port_domain -output * -async -module BIG_CPU_top
6. Waivers
I did not compare how the 0-in waiver system ("Edit Directive") worked.
The edit directive dialog box is very similar to the custom waiver dialog
box in Spyglass.
Spyglass's waiver GUI had a place to put in a comment for each waiver.
Unfortunately certain button clicks in that GUI could cause all those
comments to be deleted.
I'm worried about hierarchy or applying a block's directives/waivers up
the chain. We generally like to be able to have a low level block
designer deliver a list of exceptions to the next level up. Neither
tool supports this very well at this time.
Spyglass requires carefully crafted regexps to achieve this.
7. Reset Related Questions
Spyglass reports clock problems related to resets. I did not see any
messages for this in the 0-in output. This could mean one of two
things: my block is perfect in this regard (i.e. all required reset
re-timings are in place) or that the tool doesn't check resets at all.
I need to look into this more.
8. 0-in Gotchas
0-in may have a similar problem seen with clock_sync01 in Spyglass where
the tool reports only the first of two or more problems for a given
"rule". I did not directly observe any of this type of problem with
0-in. However, Mentor support staff was not able to definitively say
that 0-in does not report problems in this manner.
They took an action item to find out from the 0-in developers.
0-in has a bug in the way it deals with repeated VHDL code created with
GENERATE statements in one of our blocks. They have opened a ticket and
are working to fix this. The bug shows up in messages that say that
there is a CDC problem from one pin to each of the generated latches;
when in fact no such path exists. Mentor reports that small test cases
do not reveal this bug. So something to do with the size and/or content
of our RTL brings this bug to light.
I would like to have a "Copy Details" option in the right click menu of
the messages window. Doing so will let me paste the details somewhere
else. As a work around I was able to "View Details", switch windows to
the Details window, and highlight. Spyglass has "Copy" option in this
context menu. It is a very useful feature when I need to email message
to a designer.
9. Spyglass Note
Spyglass's tool is very configurable. My experience with the number of
messages and the setup of the tool is due somewhat to the way our tool
support people deployed it. Other's experiences may be different.
Overall of the two CDC tools, 0-in is in my opinion easier to use, and the
more robust and bug free of the two.
- Mike Birenbach
Qualcomm Cary, NC
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