( ESNUG 468 Item 3 ) -------------------------------------------- [09/13/07]
Subject: ( ESNUG 467 #1 ) Is it cheating if the LEFs pass the DRC check?
> You can see this if your 90 nm router starts producing 1000's of DRC
> violations when you use it at 65 nm. It turns out one "workaround" in
> an eval is to modify the foundry LEFs; a couple ways are:
>
> - go into the LEF and shrink the via sizes, in order to free up
> routing space
>
> - just delete all the advanced rules so it looks like 90 nm again
>
> Of course no designer would actually do this on a chip, because the
> design won't yield!
>
> But sometimes during the course a competitive eval, an AE with a weak
> router might do some odd things during debug, and forget to undo them
> later. So when you get your benchmark results back, it's a good idea
> to double-check just in case. And while you're at it, it's always a
> good idea to verify the reported eval timing actually meets your
> original SDC's, too.
>
> It was one vendor, multiple different benchmarks.
>
> If YOU want to poll users for this, it's sure as heck OK with me!
>
> - Eric Filseth
> Cadence Design Systems Inc. San Jose, CA
From: Matt Petkun <mpetkun=user domain=dadco not calm>
Hi, John,
Will you poll users on the guilty party in this cheating accusation, or is
it obvious to all but me?
- Matt Petkun
D.A. Davidson & Co. Portland, OR
---- ---- ---- ---- ---- ---- ----
From: Pratibha Kelapure <pkelapure=user domain=sequence not calm>
Hi, John,
I wanted to comment on Item 1 by Eric Filseth. I liked the way he pointed
out the problem without any finger pointing. Clever!
- Pratibha Kelapure
Sequence DA Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: [ An EDA Employee ]
Hi John,
I think it is better to keep me anonymous on this one.
I'm surprised to read ESNUG 467 #1. I am surprise because I think that it's
unlikey that the cheat (if it really is) can work in multiple companies. A
P&R benchmark has to pass at least the following checks:
- DRC
- LVS
- equivalence check
- STA (including DRV)
Sometimes, even the following are checked:
- IR drop and EM
- SI noise and delay
- power consumption
- maybe even yield ??
I feel that as long as DRC passed, it is not a cheat at all.
I've worked in a EDA distributor, and had done benchmarks with Apollo and
then Magma before. I've found that tool capability matters 50%, but the
experience of the engineer doing the benchmark matters the other 50%.
I can think of one situation that cheating might have happened. LEF is the
native format used by Cadence's P&R tool. Typically, we just have to run a
command to output different types of multiple via configurations and append
it to the LEF technology file. As long as there is no issue during P&R,
there is little need to examine the LEF file. But this is not the case for
non-Cadence P&R tools. Instead, a technology LEF translator is used. The
translated technology rules should be examined & many edits can be expected.
Usually, one has to refer to the DRC document to complete the translated
technology rules. Now, what happens if the LEF from the library vendor/fab
is not optimized... (Don't say this seldom happens. I have seen this from
180 nm to 90 nm LEFs from reputable library vendors/fabs in almost all
projects I worked on recently.)
Again, I think that as long as DRC passed, it's not cheating. Now, if the
DRC failed, or it's agreed that DRCs cannot be done for the benchmark, then
I wonder why the cheating is not caught by the design houses.
- [ An EDA Employee ]
---- ---- ---- ---- ---- ---- ----
From: Jeff Echtenkamp <echtenka=user domain=broadcom not calm>
Hi, John,
Saw the comment from Cadence about a vendor cheating in a 65 nm benchmark
for P&R. I'm surprised this would come up. Besides the problem of a
vendor "cheating", the bigger deal is it sounds like the people who are
running these benchmarks have them set up wrong.
Who cares if the vendor modifies the LEFs? If you are running a proper
benchmark, you should run a check DRC in a full GDS-based signoff with a
tool such as Calibre/Hercules/Mojave/PVS! This way such an error would
get revealed. Plus, in the end, these are the tools we all sign off with,
and if I'm running a benchmark and relying on a vendor's P&R tool to report
their own errors, this just seems a bit wrong.
- Jeff Echtenkamp
Broadcom Corporation Irvine, CA
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