( ESNUG 467 Item 1 ) -------------------------------------------- [07/26/07]
From: Eric Filseth <ericf=user domain=cadence bot calm>
Subject: Cadence warns that a rival is cheating on 65 nm router benchmarks
Hey John,
We're seeing a lot of people benchmarking 65 nm design flows these days,
especially for routing. We've been through a number of these things, and
I'd like to offer some advice to ESNUG readers embarking on them: when you
finish the eval, check your LEF files again!
The 65 nm design rules are more sophisticated than 90 nm rules, and take a
very good router to produce a clean design, especially at aggressive
utilizations. You can see this if your 90 nm router starts producing
1000's of DRC violations when you use it at 65 nm. It turns out one
"workaround" in an eval is to modify the foundry LEFs; a couple ways are:
- go into the LEF and shrink the via sizes, in order to free up
routing space
- just delete all the advanced rules so it looks like 90 nm again
Of course no designer would actually do this on a chip, because the design
won't yield!
But sometimes during the course a competitive eval, an AE with a weak router
might do some odd things during debug, and forget to undo them later. So
when you get your benchmark results back, it's a good idea to double-check
just in case. And while you're at it, it's always a good idea to verify the
reported eval timing actually meets your original SDC's, too.
- Eric Filseth
Cadence Design Systems Inc. San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: John Cooley <jcooley=user domain=zeroskew bot calm>
To: Eric Filseth <ericf=user domain=cadence bot calm>
Hi, Eric,
I love how you very subtly wrote this letter! Too funny! So you caught a
Cadence rival cheating on a 65 nm P&R benchmark. Want to elaborate on this
a bit more? Say who tried this? (If one particular vendor is flagrantly
cheating on router benchmarks, the users should be warned.)
- John Cooley
ESNUG/DeepChip.com Holliston, MA
---- ---- ---- ---- ---- ---- ----
From: Eric Filseth <ericf=user domain=cadence bot calm>
To: John Cooley <jcooley=user domain=zeroskew bot calm>
Hi, John,
It was one vendor, multiple different benchmarks.
I hope you don't mind but I just would rather not get much less subtle. I
think everybody will get it. If anybody is going to say "XYZ intentionally
went over the line" it ought to be the users who caught them, not another
EDA company.
But if YOU want to poll users for this, it's sure as heck OK with me!
- Eric Filseth
Cadence Design Systems, Inc. San Jose, CA
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