( ESNUG 465 Item 15 ) ------------------------------------------- [06/28/07]
Subject: ( ESNUG 454 #18 ) Yet another user yarping on EVE ZeBu emulation
> Loading an existing model into the Zebu box takes 5 minutes. Building a
> 32 FPGA model takes about 10 hours, 4 hours for synthesis, 4 hours for
> FPGA place and route, and 2 hours for the Zebu tools (logic insertion,
> partition and final merge). A 16 FPGA design might take 6 hours.
>
> ZeBu's debug approach uses the FPGAs internal scan mechanism. This allows
> us to dump out the values of all state elements. We use the Novas Siloti
> tool to map this gate level dump into RTL-level signals and to inflate the
> data so that we can examine the intermediate nodes of the design. When a
> fix is made, you can reduce the number of steps required to build a model.
>
> - Mike Dickman
> Palo Alto Semiconductor Santa Clara, CA
From: Kevork Kechichian <kevork.kechichian=user domain=lsi bot calm>
Hi, John,
Our initial ZeBu-XL bring up took on the order of 2 weeks to get the design
and some of the transactors operational. All follow up development was
incremental and did not require significant effort. During that time we had
full, efficient support from the EVE team.
Our initial eval was for 2 designs. The first design was 400 K gates, and
we used it to measure the highest frequency possible on a ZeBu, 7 MHz.
The second design was 2.2 M gates, which we ran to test ZeBu's capacity.
The main clock was running at 3 MHz. In both cases, we were able to hit
a high operating frequency and capacity in terms of advertised gates versus
real gates.
We mostly used ZeBu-XL's C/C++ co-emulation model. We liked the flexibility
EVE allowed us in moving between its operational modes as our requirements
changed, e.g. Verilog acceleration and transaction-based co-emulation.
EVE's new RTL front end lets ZeBu users start the compilation flow from RTL
code. It automates the RTL-to-ZeBu compilation process. Previously, our
starting point was a Verilog gate-level netlist, and the users had to get
there by running Design Compiler by hand.
ZeBu's debug functionality aligned very nicely with what our designers had
been exposed to on VCS. The interface was very intuitive to use, and it
allowed full visibility into the design. We were able to narrow down
the verification issues very quickly using the static versus dynamic
approaches, along with the various trigger point setting features.
Mapping embedded memories onto ZeBu resources is a bit restrictive. I
suspect this is not specific to Zebu or EVE however. Having said that,
EVE's support for generating memory wrappers and automating the mapping is
pretty good, and generating them required minimal intervention.
The two aspects of ZeBu-XL that helped us the most were:
a) The acceleration. It allowed us to reduce our regression iteration
times by 3 orders of magnitude, and allowed us to test multiple
scenarios. Our regression runs, on one of the modules, went from
months, on a Linux farm, to just under a day on the XL system.
b) ZeBu's ability to scale. It allowed us to integrate complete
sub-systems, and test them in real application frameworks. It also
allowed us to test some of our SW code early in the design cycle.
ZeBu's biggest strength is the software environment it offers, from
development to debug. We were very pleased with the maturity of the API and
its flexibility.
- Kevork Kechichian
LSI Logic Toronto, Canada
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