( ESNUG 465 Item 8 ) -------------------------------------------- [06/28/07]

Subject: Synopsys says Vera won't be EOLed, instead Vera will be enhanced

> Hi John,
>
> I heard the rumor that VERA is going to be end of life.  Is it true?
>
>     - Alicia Strang of Marvell Semiconductors


From: George Zafiropoulos <georgez=user domain=synopsys bot calm>

Hi John,

Vera continues to be a very popular testbench automation product used by
many of our customers.  Of course, we will continue to support all popular
languages including System Verilog, VHDL, SystemC and Vera.  There are no
plans to end of life Vera.

We are continuing to invest in Vera, enhancing the language, adding new
performance and productivity features, and advancing the methodology.

For example in the latest release we delivered the following...

  - Improved constraint solver / randomization
  - Dynamic Allocation: resizable arrays grow and shrink
  - Debug coverage GUI support
  - Specify transition bins using state bin names
  - New reporting capability

Simply put, Vera is widely used and we continue to invest in it.

    - George Zafiropoulos
      Synopsys, Inc.                             Mountain View, CA

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)