( ESNUG 465 Item 4 ) -------------------------------------------- [06/28/07]
From: Frank Chen <fchen=user domain=micron bot calm>
Subject: Cadence NC-Verilog 5.6/5.8 SDF has some funky annotation problems
Hi John,
I have a question regarding NC-Verilog 5.6/5.8 SDF timing annotation on
input nets connecting to bi-directional primitives such as tran, rtran,
etc. To make things more clear, let me give you an example:
module A (input a, output b);
B instance_b (a, c);
assign b =3D c;
endmodule=20
module B (inout a, inout c)
tran (a, c);
endmodule
When I'm trying to perform an input port annotation hierarchically on A.a,
the annotation would not work, no errors or warning at all. The timing
refuses to be annotated unless I add an additional buffer before module B,
modifying the code to:
module A (input a, output b);
wire d;
buf instance_b (d, a);
B instance_b (d, c);
endmodule
I understand that primitive bi-directional switches do not allow timing to
be annotated, but in my case, I'm annotating the input node *before* the
primitive, yet it is still not annotated unless a unidirectional gate is
placed in front?! Do you know if this is a bug in Cadence? I have not had
the chance to try this on Synopsys VCS.
- Frank Chen
Micron Technology, Inc.
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