( ESNUG 464 Item 8 ) -------------------------------------------- [03/30/07]
Subject: ( ESNUG 461 #6 ) The Freescale first impressions of Cadence ETS
> I've seen nothing on my end either. It's been close to a month. Since
> no users have replied so far, it's my guess that Cadence is trying to get
> you to be the test guinea pig for their new ETS-XL sign-off tool. I find
> it odd that instead of being open about it, they appear to be trying to
> "trick" you into using it. Usually EDA companies are mostly open about
> having someone volunteering to be a beta customer.... Odd...
>
> - John Cooley
> ESNUG/DeepChip.com Holliston, MA
From: Jason Perez <jason.perez=user domain=freescale not palm>
Hi John,
So far at Freescale we have been evaluating Cadence's ETS for several months
but as of now have not taped out a chip using ETS for signoff. However on a
production chip we are working on now we fully intend to use ETS for signoff
STA timing.
ETS itself was easy to start doing timing analysis, mainly because it was
able to read in most of our existing scripts and constraints with minor
modification. Since it's Tcl based it's also easy to write new scripts.
We have run both non-signal-integrity and signal-integrity (SI) runs. The
accuracy of the tool for both runs compares well with what we expect. For
SI accuracy one needs to understand and set the extraction and SI filtering
parameters to represent your design and process.
For a 456K instance design with 557K nets:
Cadence ETS non-SI runtime: 15 minutes
Cadence ETS SI runtime: 3 hours
A plus is the common timing engine (CTE) used for both First Encounter and
ETS. What this means is that the correlation between the P&R timing and
signoff timing will be tighter. Also ETS supports ECSM libs so it will be
possible to do IR-drop using reports from Voltage Storm.
For optimal runtimes a QRC based extraction is preferred. The numbers I'm
quoting are from QRC extractions.
Cadence ETS non-SI memory footprint: 3.0 Gbytes
Cadence ETS SI memory footprint: 9.5 Gbytes
Cadence needs to improve this number. For a chip 2X the size of what I
have, the memory footprint is getting prohibitive.
- Jason Perez
Freescale Semiconductor Austin, TX
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