( ESNUG 464 Item 7 ) -------------------------------------------- [03/30/07]
From: Frank Chen <fchen=user domain=micron not palm>
Subject: Cadence NC-Verilog SDF annotation won't work on bi-directionals
Hi John,
I have a question regarding Cadence NC-Verilog 5.6/5.8 SDF timing annotation
on input nets connecting to bi-directional primitives such as tran, rtran,
etc. To make things more clear, let me give you an example:
module A (input a, output b);
B instance_b (a, c);
assign b = c;
endmodule
module B (inout a, inout c);
tran (a, c);
endmodule
When I'm trying to perform an input port annotation hierarchically on A.a,
the annotation would not work! No errors nor warning at all! The timing
refused to be annotated unless I add an additional buffer before module B,
modifying the code to:
module A (input a, output b);
wire d;
buf instance_b (d, a);
B instance_b (d, c);
endmodule
I understand that primitive bi-directional switches do not allow timing to
be annotated, but in my case, I'm annotating the input node *before* the
primitive, yet it is still not annotated unless a uni-directional gate is
placed in front? Do you know if this is a bug in Cadence?
I have not had the chance to test this on Synopsys VCS.
- Frank Chen
Micron Semiconductor Shanghai, China
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