( ESNUG 464 Item 1 ) -------------------------------------------- [03/30/07]
From: Stu Sutherland <stuart=user domain=sutherland-hdl not palm>
Subject: Cliff & Stu fighting over the default_nettype compiler directive
Hi, John,
Cliff Cummings and I are having a very vocal disagreement over this and it
would help if you ran this in ESNUG ASAP.
Has anyone had any experience using Verilog-2001's
`default_nettype none
compiler directive? This directive turns off Verilog's implicit net
declarations, thereby making it necessary to explicitly declare all wires
used in a module.
Did using the directive solve problems in your Verilog code, or did it
create new problems? Or did you use it just because you like having to
declare every single wire?
(I'm trying to phrase the question neutrally so Cliff doesn't accuse me
of trying to influence the results.)
Getting the users' replies ASAP would help a lot. We need it to settle
something we're presenting at next week's San Jose SNUG.
- Stu Sutherland
Sutherland HDL, Inc. Tualatin, OR
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