( ESNUG 463 Item 7 ) -------------------------------------------- [03/16/07]
Subject: Answers from Brett Cline, the SystemC Poster Boy
> For the last few years you tell us that next year will be the year of
> SystemC. So, will next year be the year of SystemC?
> Is there any future for SystemC? Apart from Forte who seems to be selling
> the concept of using SystemC as behavioral synthesis entry, the SystemC
> Community doesn't seem to be expanding.
Actually, LAST year was the anchor year for SystemC. In 2006, most of the
largest systems and semiconductor companies deployed SystemC for design,
verification, or both.
Many people assumed that "the year of SystemC" would be the year in which
everybody starts using SystemC *instead* of Verilog and VHDL. But that
isn't the way things work in electronics design. We don't throw things
away -- we just build on top of them. Just as we haven't thrown away
GDSII, gates, etc. we won't soon get rid of RTL.
It became clear in 2006 that at the system level, SystemC is the common
denominator that ties everything together -- not just for ESL but also for
hardware design beyond RTL. Almost every EDA company, and many semi and
systems companies, with proprietary solutions in the system space have
either moved to SystemC or built bridges from their solution to SystemC.
And Forte is not the only vendor supporting SystemC - and the community
continues to expand.
Consider these stats for 2006:
NASCUG meeting attendees: 95
SystemC TLM tutorial attendees: 100
OSCI membership: 31
system and semi companies in OSCI: 10
SystemC downloads: 297,000+
SystemC registered users: 45,000+
And the NASCUG corporate members names are getting bigger:
ARM Ltd.
Cadence Design Systems, Inc.
CoWare, Inc.
Forte Design Systems
Intel Corporation
Mentor Graphics Corporation
NXP Semiconductors
STMicroelectronics
Synopsys, Inc.
NASCUG associate corporate members:
Actis Design, LLC
Atrenta, Inc.
Bluespec, Inc.
Broadcom Corporation
Calypto Design Systems, Inc.
Canon Inc.
Carbon Design Systems
Celoxica Ltd.
ChipVision Design Systems AG
Denali Software Inc.
Doulos Ltd.
ESLX, Inc.
Fraunhofer Institute for Integrated Circuits
Freescale Semiconductor Inc.
GreenSocs Ltd.
JEDA Technologies Inc.
Infineon Technologies AG
NEC Corporation
SpringSoft, Inc.
Synfora Inc.
Tenison EDA
VaST Systems Technology Corporation
New SystemC products are announced every year and even Cadence pre-announced
some sort of SystemC synthesis product on the Troublemakers panel this year.
(Thanks for that tidbit, Ted!).
---- ---- ---- ---- ---- ---- ----
> Is Forte in trouble? Why did they lose their second CEO in less than a
> year? He joined in January, left in December.
> Why did you new CEO leave so soon? What does he know that we don't know?
In December 2006, Forte announced that we promoted Sean Dart, our VP of
engineering, to president and CEO. Sean replaced David Sear who had joined
Forte in 2005. David came from the semiconductor industry and had been
tasked with organizing the company for success and raising money. David
succeeded at the tasks he was given and we closed $5.4 M in Q3.
We had expected that David would also be the one to drive the company
forward after getting funding. However, for a number of different reasons,
the board and David agreed that Forte needed an EDA technologist that knew
the market, the product, and the people.
Sean has been with Forte since we were first formed in 2001. He's overseen
product development and deployment, has a great relationship with our
customers, and has a clear vision for where ESL is going and Forte's part in
driving it. (Did I mention he's my boss so I probably should also say what
a cool guy he is?)
---- ---- ---- ---- ---- ---- ----
> I see more than 20 customers a month, a lot of them startups pursuing very
> aggressive design targets - why no ESL there? Nobody is using it.
Hmmm. We must be talking to different companies. We spend a lot of time on
the road each month as well, and we are seeing completely different things
in the market. For instance, in the US, we are currently working with a
small startup company that determined that by using Cynthesizer for
behavioral synthesis along with the free OSCI SystemC simulator and
Synplicity's Synplify Pro, they can inexpensively model, simulate and
implement their entire hardware design, including having a quick proof of
concept, with good results. This is just one example, but there are more.
If you look at the OSCI membership list (above) you'll notice that there are
a lot of US-based companies getting active in SystemC.
There is one last point - it's important to separate SystemC hardware design
from ESL. Designers today utilize SystemC-based hardware design for
improving their hardware process, even if they don't choose to design the
whole system top to bottom using a new methodology like ESL. So, while
people maybe using SystemC for verification and hardware design it doesn't
necessarily mean they have moved to "ESL".
Ask yourself this: Do you really believe that RTL Verilog is the final
frontier for hardware design? If you do, "good luck bro." If you don't,
what's next if it isn't C-based design?
---- ---- ---- ---- ---- ---- ----
> Can Forte make money by any means other than selling off parts of the
> company? (referring to the sale of the Chronology division to EMA)
TimingDesigner was a profitable business that we sold it because it had no
synergy with our SystemC synthesis business and it was a great strategic fit
with EMA. We are now taking resources that were split between 2 orthogonal
products and markets and focusing them in an emerging area where we have a
leadership position. The timing was perfect for us because we've got a
sustainable, growing revenue stream with Cynthesizer.
---- ---- ---- ---- ---- ---- ----
> Is it true you are losing market share in Japan to Mentor Catapult C?
Categorically, NO. Forte is holding its leadership position in Japan. Our
customers in Japan are production users and most have been with us for the
better part of 5 years. Each year we add more customers than any other
high-level synthesis vendor in Japan and will do so again in 2007.
---- ---- ---- ---- ---- ---- ----
> Why did Forte fail in the Bluespec design challenge?
> Why did you duck the Bluespec design challenge?
> Bluespec is giving you a good run for the money. How do you plan to deal
> with them?
> How many customers have you lost to Bluespec lately?
> Hey Brett, why not take the Bluespec design challenge? Chicken?
Calling me chicken, eh? I think I've lived up to that one already when I had
to wear the chicken suit at DAC 05 from losing my SystemC bet with John.
Before I answer, I'd like to thank the entire team from Bluespec for
spending their copious free time plugging themselves with these questions!
You know, this one is really simple - I call it "the ol' EDA dual". This is
when one small, lesser known company, needs to find a way to become known,
so they try to attack someone bigger than them to create some controversy.
It is a lot like the hyperactive 4-year old at a family party. The need for
attention becomes so great that they find the biggest kid in the room and
kick him in the shins to try to get a reaction.
The reality is while they have engineers in the back room cooking up canned
examples, Forte is dedicating its resources to real customer designs. We
are always ready to compete on real projects at real customers.
Rather than sniping at each other, I would prefer to see the companies that
claim C, SystemC, or ESL synthesis work to build the SystemC-based design
market. Now that would be the real win for the industry.
---- ---- ---- ---- ---- ---- ----
> Does Celoxica's recent "re-focusing" on "accelerated computing" and away
> from ESL synthesis mean that the current crop of ESL synthesis tools is
> dead? Or is the field too crowded? What makes Forte think it will be a
> survivor, now that Celoxica has voted itself off the island? Who else is
> about to be voted off?
Ok, there are actually 4 questions here:
1. If you take a really good look at Celoxica's technology you would see
that this is a good move for them. They've got a lot of IP in the FPGA
board space and their technology caters to a different market. Celoxica
was already competing in a different market.
2. Is the field too crowded? Definitely. Like all new technology areas in
EDA, a lot of companies emerge with marketing messages that begin to sound
alike. Many of the small companies probably have 1-2 customers that look
promising and allowed them to get their initial funding, but the reality is
most of these companies won't make it through the next 2 years.
3. Forte will be a survivor because we already have critical mass and wide
adoption in the user base. Cynthesizer is being standardized are several of
the top 10 semiconductor and systems companies worldwide. Our customers
have gone to market with 30+ ASICs and SoCs with Cynthesizer to date.
4. The next group to get voted off the island will be companies with a
proprietary solution that doesn't plug into the rest of the design flow.
The market just doesn't accept that. Several are on their way out now.
"Bring me your torch, the tribe has spoken."
---- ---- ---- ---- ---- ---- ----
> What's holding back ESL adoption? When are we going to have customers
> take over the Poster Boy job? Where is the adoption?
Customers are taking on apprentice-Poster Boy positions as we speak. Just
take a look at the NASCUG (www.nascug.org) meeting at DVCon. The panel
consisted of representatives from Emulex, HP, Intel, Motorola, and TI
talking about what's working and what they'd like improved. At Forte's
recent Cynthesizer User's Group conference OKI, Toshiba, Ricoh, and others
presented their successes in a public forum.
Adoption is happening. Certainly in Japan and Europe, and now it is also
making its way through Korea, the US, and the rest of the world. The
research that we've done shows that that the main differences between the
US versus the ROW are:
1. In Japan, the primary issue is time to high quality RTL - productivity.
This fits very well with the traditional SystemC/behavioral synthesis
value propositions.
2. In the US, Joe Q Design Manager sees his problems more in timing closure
and verification. It isn't completely clear to him how technologies
like SystemC synthesis can help him overcome these issues, but we see
benefits there also.
Verification with SystemC is simply better. SystemC-based models are easier
to write and simulate much faster than RTL Verilog models.
As for timing closure, Forte's customers use Cynthesizer to help achieve it,
end of story. Cynthesizer has the freedom to generate any datapath it wants
and to produce the control logic to manage it. It knows clock speed, the
technology library (and therefore datapath parts) and will produce RTL that
meets timing. This eliminates a painful part of the problem of RTL design
that typically causes months of delays.
We're taking it even further. At the DATE conference in Nice, Forte's plans
to show integration with Magma's Blast Create that takes high-level SystemC
code and goes right to P&R, giving designers the most accurate estimate of
timing and area they can get MUCH earlier in the design process. So, now as
they do architectural exploration with Cynthesizer from SystemC they can
figure out which design will give the best P&R utilization before.
And, if the timing ends up to be too close for comfort, Cynthesizer can be
constrained to have slack in the cycle, regenerate the micro-architecture,
and meet more aggressive timing needs - without rewriting any code.
To be able to figure out how routable a design is without spending months
writing RTL is revolutionary.
---- ---- ---- ---- ---- ---- ----
> First you have to deal with System Verilog. Now you have an ANSI-C and
> SystemC for ESL debate going on? In addition, Bluespec is sniping at
> you. How are you dealing with getting hit from 3 sides?
The SystemC versus System Verilog debate is largely over. People that are
using System Verilog are doing so for either RTL design or for verification;
though there is some confusion among the vendors on which exact version of
SystemVerilog each supports causing flow problems. There are some design
benefits in System Verilog but the abstraction level is essentially still
RTL.
For behavioral-level/C-based design - the level above RTL - the debate has
really been focused around SystemC or ANSI-C/C++.
1. ANSI-C isn't viable for hardware design and system design. At first
blush, it looks fast and easy - but there is a reason for it. There is
no way to model concurrency. Even John Cooley has built designs in the
last few years that require some sort of concurrent operation. So, you
end up with code that doesn't accurately model the behavior of the
design. Is that what you want to verify? Other issues exist too: Bit
accuracy, timing accuracy, and support for single standard.
2. With SystemC, which IS C++, you get all of C++ plus standard features for
hardware and system design.
- Using transaction-level modeling (TLM) you get fast, accurate
designs that model the exact behavior of the hardware
- Concurrency, bit accuracy, timing accuracy, hierarchy, etc.
- Support for a standard - simulators, analysis tools, debuggers,
synthesis tools, etc.
So, when you compare languages, look beyond the simple FFT test case to what
your design is really going to look like. You'll find that SystemC is the
only language that covers all of your needs for design and verification at a
higher level of abstraction.
---- ---- ---- ---- ---- ---- ----
> Brett: "It takes 6-7 months of C++ training and pilot projects to get
> someone proficient (not an expert) in C++. Why take a great Verilog
> engineer to make him a mediocre C++ programmer?"
You aren't ruining a great Verilog engineer, you are making a great hardware
designer more productive. (And exactly when did "hardware designers" become
synonymous with "Verilog engineers"???)
The generally accepted number of verified gates per year is about 300,000
for an engineer using RTL (or 25,000 gates/month). By comparison, one of
our customers is currently doing a 5 M gate SoC w/ 8 designers in 5 months.
I'll do the math for you, John. It's 125,000 verified gates/month.
That's a 5x difference! And, during the process they are eliminating the
typical timing closure problems encountered with an RTL design flow and
creating behavioral IP which is much more reusable than RTL.
Another customer had both a very junior hardware designer that was an expert
in C++ and a senior hardware designer that knew very little C/C++/SystemC.
When it came to getting the best hardware QoR in the fastest time, the
hardware designer won.
So, if you are a great hardware designer now, you'll be an even better
hardware designer when you move to SystemC and Cynthesizer.
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