( ESNUG 463 Item 6 ) -------------------------------------------- [03/16/07]
Subject: Answers from Atul Sharan, CEO of ClearShape
> You and Cadence are temporary Brokeback buddies in DFM. Who pitches?
> Who catches? How long before you see this deal ending?
As I said in person on the panel this is in the category of dumb questions.
Nevertheless let me answer what I think is the intent of the question. We
have an excellent partnership with Cadence driven by customer need to
integrate our DFM tools into Cadence Physical Design tools. Our tools are
architected to work in ANY design flow so our success is not dependent on
'integration'. However customers, in general, are demanding that physical
design tools be DFM aware.
To be clear, this is not Hollywood or baseball so there are no Brokeback
buddies, no pitching nor catching.
But if the person who came up with this question chooses to disclose their
identity to us, we will send them 2 free movie tickets and 2 free tickets
to an A's or Giants baseball game.
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> Your tools are point tools. To be useful, they need be integrated to P&R,
> layout tools, timing tools, and extraction tools. So far Cadence claimed
> that your InShape integrated with its Chip Optimizer, BUT the integration
> is to go through DB file transfer then batch-run InShape then ASCII hot
> spot result back. This is dumb. So what is the problem? Cadence or you
> unwilling to co-operate?
This flow is being used in production tapeouts today. There is no penalty
in this flow as you've suggested, and in fact InShape can be called from
within Chip Optimizer. InShape's also integrated into Silicon Canvas Laker.
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> You raised second round of funding, you have not been acquired yet and the
> third round is key for an EDA startup. So what is up with ClearShape?
> Anything wrong with the value proposition, any skeleton in the closet?
Clear Shape's lead investor is USVP, a leading Silicon Valley venture firm
that was also a lead investor in Brion. We also have corporate investors;
the ones we have disclosed are Intel (who led our Series-B), KLA-Tencor and
Cadence. As far as we know, we are the only DFM company to date where Intel
has invested. Access to money is not an issue for us. Obviously if we've
gone as far as we have without yet raising a 3rd round of funding, then
surely we must be getting revenue? Enough said.
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> For Atul Sharan - There is a defined trend to using Reduced Design Rules
> (RDRs) for physical IP libraries. When the majority of the market adopts
> these technologies at 45nm and below, what will your company do since the
> need for your type of tools will be eliminated?
RDRs have been discussed since 130 nm. From our stand point the future will
be a combination of Rules + Models. By definition this whole tiering of
rules into recommended rules, restricted rules, etc. means that you are
giving up something and making a tradeoff leading to insufficient use of
silicon.
Of course there'll be 'rules' amalgamating some restricted rules. However,
as Sunit Rickhi of Intel says, ultimately DFM is all about maximizing the
value of the process platform -- in which case every 'extra' rule detracts
from full utilization of your process platform. If designers want to
accept grossly inefficient use of silicon, they will accept a plethora of
RDRs. But, I believe designers are much smarter and they will demand and
use a combination of rules (including as few RDRs) and model-based tools.
The fabs that over-restrict designers and severely limit their flexibility
will not be the economical winners. Model-based design methodologies are
imperative, all you have to do is look downstream: Why is model-based OPC
so dominant when a few years ago you could do with just 'rule'-based OPC?
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> In a head-to-head runoff's with RET flows from suppliers for DFM testing,
> surely an inexact compact model (as you are proposing) can never provide
> the accuracy for identifying all the layouts with printability issues that
> an exact form can provide. Your inexact forms are clearly preferable over
> nothing as they can point out classes of obviously bad layout configs.
>
> But it is inevitable they will miss some, this may be excused for such a
> new technology. With increasing complexity at advanced nodes - double
> patterning, etch models, complex OPC scripts and maybe even inverse
> lithography more cases are going to be missed and with such an inexact
> representation.
>
> Wouldn't you agree customers will demand no critical errors are missed
> and your inexact flow won't have the legs to support this?
ClearShape has shown extremely close correlation to actual silicon over
98.5% in many instances -- with added advantages of being full-chip,
extremely fast, OPC tool-independent, and fully endorsed for all layers by
all major foundries. However, we are flattered our competition chooses
to create FUD around this.
InShape has been qualified at 90, 65, 55 and 45 nm. It has consistently
proven to be extremely accurate and the only tool that can do accurate and
fast full-chip analysis in hours. (For REAL NUMBERS, please take a look at
http://www.deepchip.com/items/else06-22.html, where users wrote in as =
early as last summer and since then the tools have only improved!)
Having a model tied to doing OPC-inside is just not feasible -- all the
information required to do that accurately will never be released by
foundries; even if it were it would take 5-7 days/layer to run OPC. If it
could be done faster, then the major OPC suppliers would have sped up their
OPC a long time ago -- which hasn't happened in spite of their proprietary
hardware use. The beauty of ClearShape's formulation is that we're agnostic
to the OPC tool or RET technique being used and are able to focus on what is
important to the designer.
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> Last year you commented on who would survive the DFM deathwatch list...
> Who are your current bets on surviving for this year? Who's going to die?
Emerging markets inherently have flux. The DFM start-up failures -- and yes
they will come -- will probably be because:
1. Traditional EDA Vendors are trying to package post-GDSII OPC solutions
into DFM solutions.
2. Companies pushing rule based solutions and trying to capture DFM issues
without foundry data to capture real silicon information.
3. The fabs won't be able to support dozens of EDA vendor products.
As Mike Santarini suggested recently, designers can look to the foundries to
spot which EDA vendors have qualified tools. Further, as George Orwell
(though not an EDA icon) once said, some are 'more equal than others'. In
the case of DFM, it will be the EDA vendors that are qualified by foundries
AND are being used by real design teams.
I think perhaps Synopsys and maybe Mentor only of all companies may be able
to field partial solutions based on their post-GDSII OPC, but these will not
gain widespread acceptance -- being sold primarily by creative bundling in
3-year deals. You can only fool some of the people some of the time. :-)
ClearShape will do well, and I wish everyone else good luck!
---- ---- ---- ---- ---- ---- ----
> Why did ASML buy a DEATHWATCH company Brion for $270M (almost the same as
> Magma's market cap) even though they were losing money? After all, Brion
> competes on OPC verification with Synopsys and Mentor.
The last few years saw the lithography-plane being extended to include the
mask/RET/OPC etc. (post-GDSII). It is clear that for the industry to march
down the path of Moore's law, the lithography challenges will require
litho-aware design. The litho-plane is now extending to include physical
design. ASML is a stepper company and they must control, influence or
otherwise manage the entire ltho-plane to effectively sell steppers. The
first step is the move into OPC Verification (and OPC).
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> There are 20 or so DFM companies. 3 to 5 will be bought by somebody on
> this panel, the rest will struggle or disappear altogether. What's going
> to happen to you and why? Can you really go public with a DFM tool?
Currently we are focused on building our products and creating value. Our
opinion is that design implementation tools must inevitably become
model-based-DFM smart or slowly get marginalized in value. As was clear
with the acquisition of Brion (would anyone have predicted that ASML would
pay $270 M for Brion a year ago??), the boundaries and the roles of
different stakeholders in the supply chain are changing. Those with a
strategic view of creating new markets will seize this opportunity; and
those who continue to look at this with the jaded EDA lens will always see
the glass as half empty. DFM has the potential to alter the landscape in
fundamental ways. A case in point is TSMC's extraordinary leadership in
creating a DFM ecosystem and making available information and tools to their
design customers -- even as recently as a year ago some people predicted
'foundries' would never do this.
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> It seems that 65 nm node is not showing the concrete need for litho
> simulation like your InShape. How does a startup survive when large
> companies like Mentor and Synopsys have litho sim and they can add
> this type of technology part of their large deals?
This is a general malaise afflicting the EDA industry. We have seen sales
cycles being drawn out because of zero-$ addition of tools, foil-ware and
high-level promises. Ultimately customers realize they get what they pay
for and merely shoving in manufacturing-tool-dependent, slow and inaccurate
(for design side use) post-GDSII OPC tools and litho-simulation on the
design side into 3 year deals doesn't solve real technical problems or
improve yield or ROI.
Unfortunately the bigg EDA vendors have only paid lip-service to price
discipline and beggar-thy-neighbor still seems to be the prevailing mantra.
Look at the history and count where the revenue for the large companies
comes from. Wally Rhines has been vocal in stating that innovation comes
primarily from start-up companies. This was true the last 10+ years and
will be true for the next 10+ years.
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> DFM is an important space but the market has not caught up with the need
> for this technology yet. How will you survive during this low period and
> come out as an independent company, or is that even in your plans?
This is not a low period in the sense that the market demand is on the rise.
You just have to plan so that you do not get ahead of the curve. We have
been extremely capital efficient and with the revenue we have coming in we
are well positioned to capitalize on the DFM growth.
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> DFM point tools are not in TSMC's or any foundry's reference flow.
> There's still lots of debate about DFM being who's cost. What's your
> exit plan? Do you see TSMC's DFM design service with their own internal
> developed tool as a competition?
DFM tools (ours at least) are part of TSMC's certified DFM flow. None of
our efforts compete with any TSMC internal development as far as we know.
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> Do these guys, especially Atul, see litho sim and other manufacturability
> assessment tools ultimately replacing traditional, rule-based DRC
> checking, as design rules transition from digital (pass/fail) to analog
> (contextual)? If so, when? If not, why not?
Absolutely. In fact it is already happening. As 65 nm really ramps into
mainstream you will see a big up tick in the adoption of such tools. These
model-based tools are being used at 65 nm and will in fact be the 'default'
methodology at 45 nm. The competitive bar will be set by these early
leading-edge adopters and the mainstream will necessarily follow.
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