( ESNUG 463 Item 3 ) -------------------------------------------- [03/16/07]
Subject: Answers from Joe Sawicki, GM of Design-to-Silicon, Mentor
> What happened to their new emulator ("Diamond/Veloce") that they announced
> at DAC 2005 which is over 1.5 yrs ago.
Veloce wasn't announced last year, it is going to be launched at DATE 2007
in April. Check out the January 22nd issue of EEtimes for Broadcom's
experience with Veloce. If you're interested in emulation, you should
be talking to us at Mentor.
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> Is Mentor waiting for the Synopsys-Magma lawsuit to settle first before
> it tries to acquire Magma?
What a great question! Because I'd love to discuss Mentor's M&A strategy in
a public forum! Seriously, you can't expect us to talk about what we will
or won't do in M&A.
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> When are you going to buy Sierra and enter the P&R market? Sierra seems
> to be very promising in the "IC implementation" space, and they already
> work closely with Calibre LFD input. Wouldn't this fill in the Mentor
> DFM router picture? Are you guys haggling over price?
Same answer as the question on Magma.
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> Joe Sawicki (Mentor) - We keep hearing rumors that Mentor is making a
> play in the P&R space but we haven't seen anything yet. When will
> Mentor acquire back-end technology or do you think having a solution in
> the back-end flow unimportant?
Mentor has focused our business on a couple of areas where we can provide
designers with some compelling tools. Back end verification and DFM,
functional verification, PCB and a few others. We're not convinced that
designers want one stop shopping if that means they have to take inferior
tools. We think our success says that we're right.
So when I get asked, 'why aren't you selling a tool in category X?' my
answer is that we won't sell a tool in a category if we can't make a
compelling difference.
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> Why does the Calibre LPE do such a bad job at extracting inductance, even
> though Mentor often advertised that this is the best LPE tool?
This one surprises me. Our inductance tool has been getting some fantastic
results on accuracy vs. both fast Henry and Silicon.
What has been more of an issue has been integrating inductance extraction
into existing design flows. This usually ends up hitting up against issues
in how the libraries are set up, but they are surmountable hurdles.
If you're having issues, a local AE or our support organization can get you
there faster than an email in for a panel question. If that isn't working,
send me an email.
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> Mentor recently announced that its latest Calibre nmOPC product would run
> on a Cell Broadband Engine-based computer from Mercury Computer Systems.
> EDA's history is littered with the dead carcasses of HW accelerated apps
> such as this. Is this for real or is it just a PowerPoint slide? If
> real, why will this succeed when most HW accelerated applications in the
> past have failed?
It's absolutely real and the partnership with Mercury was critical to us
getting this project complete on time and on performance target.
As for the question on why this is different from HW acceleration in the
past I'd bring up 2 points. First, this is not custom hardware, this is a
standard compute platform that just happens to have a cell processor rather
than an x86. It is being used in a number of other applications (medical
imaging and oil exploration were the first) all of which have in common
that they involve solving massive amounts of FFT's. We didn't design
custom hardware; we ported part of our application to a different computer.
Second, we did this in an open, user-configurable, non-propriatary system.
You can run nmOPC on a pure x86 cluster, or you can add Cell BE blades to
accelerate the performance of that system by about 4x to 8x.
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> Sawicki - How does Mentor's hardware-based OPC compare to that of Brion?
That's really covered in the previous question. We're based on a flexible,
standard compute platform. Brion is based on proprietary hardware. Frankly
the Brion guys did a good job of brining their system up, but we believe
our approach provides a much more interesting cost of ownership model for
the customer.
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> I sure would be happy to hear the Mentor guys explain what they plan to
> d owith Summit products like "Panorama". (I used to be one of the
> developers back when it was still "CARDtools".)
Mentor acquired and is offering 3 of the 4 Panorama technology components,
but the CardTools (NitroVP) piece was not acquired... therefore we won't
be doing much with it.
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> What tools besides the Calibre platform is included in Mentor's term
> "Design-to-Silicon"? And if there are other tools included, how much
> revenue do they create (relative to Calibre) and how much R&D resources
> does Mentor spend on them?
If we are talking about the division named "Design to Silicon" that is
purely the Calibre Platform. If we are talking about where we use the
term in our revenue reporting, that is primarily the Calibre platform
and our ICStation full customer design solution.
On the R&D spending, I think I'll pass on the opportunity to change the
way we do our financial reporting to satisfy someone's curiosity, but
will say that we have both long term and significant new customers that
are happy with the value we are delivering with that R&D.
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> Does Mentor believe in making $$$ with FPGA tools?
Mentor does make money from FPGA design tools and we remain hopeful that
the market will grow. At Mentor, FPGA design tools are part of larger
scale customer solutions, such as Integrated System Design and ASIC
verification. Today, too many designers in the space are locking
themselves into their vendors by using their proprietary tools. It
saves them money in the short term, but they lose the ability to trade
off target devices easily... Which can be much more expensive in the
long term.
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> Do you think a VHDL200X (or VHDL20XX) will ever exist?
There already is a VHDL 2002. And Mentor is heavily involved in further
versions of the standard.
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> In a recent DesignCon panel, it appears that the ramp to revenue for DFM
> products is moving quite slowly. Yet, you went on record awhile back at
> an investor conference that DFM revenue would be near $1.5 billion by
> 2010. How do you reconcile these contradictions?
I'd been on a fool's errand for a number of years to get people to stop
talking about DFM as if it were one thing.
At the Canaccord Adams DFM conference I inverted my usual approach and
instead just took everyone at their word. I went onto web sites and public
company financial reports to discover what tools were being called DFM by
other people.
The list was extensive and included: DRC, LVS, Physical Analysis; TCAD;
Extraction; Yield Ramp, Mask Data Prep; OPC; OPC verification; Litho
Analysis; Yield Analysis; DFT; Chip Polishing; Manufacturing Aware Routing;
and Cell Swapping.
A long list, and I'm sure a bit more Google-ing could put a couple of more
things on the list.
I then organized these tools into three categories: Old School (thing like
DRC and Physical Analysis), Manufacturing-For-Design (things like OPC and
Yield Ramp), and Design Focused (like litho analysis and yield analysis).
If you then look at these markets, pulling from public and private data, it
was easy at the time to come up with approximately a $720 million dollar
market in 2005. Of course the VAST majority of this market is in the Old
School and MFD categories.
I then did a very silly, but reasonable assumption to map the future market.
I used the 2004 to 2005 growth rate for Old School and MFD to project out
into the future, and then assumed that the Design Focused category would
follow the growth trajectory of the most successful new product category EDA
has seen in a while-OPC.
Doing this leads to an approximate $1.5 billion market in 2010.
Of course the Design Focused part of this is still less than 10% of the
"DFM" market at that point.
The reason why companies like Mentor and Synopsys are excited about this
market is that between the 2 of us we had about 64% of the market in 2005.
Just to be clear, I've no desire to be the next Dataquest (which seems wise
since Dataquest doesn't want to be the next Dataquest, at least for EDA).
If someone else has different numbers, I'm just going to agree with them
and move on.
That said, I think the analysis is pretty close.
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> Joe Sawicki: Every time anyone talks to you about your products, you
> tell them you are the best and there is nothing like it in the market.
> So, why don't you own 100% of the DFM/LVS/DRC market?
Lots of reasons that a tool that is a defacto standard does not get to
100% market share. Some part of it is due to the fact that some
designers are still doing some quantity of chips at larger feature
sizes. I'm not aware of a single 500nm chip that was run on Calibre.
There are also companies that went with one of the other hierarchical
tools when the market moved off of Dracula. We've converted many of these,
but not all. We are continuing to gain new adoptions with the new nmDRC
tool, having gotten about 25 new logos in the last quarter and about 90
logos during 2006.
I think the corollary to this question is more interesting and I'll leave
it as an exercise for the reader: If Calibre wasn't the best tool in the
market, why would we have any market share at all given that every design
creation company has a Calibre competitor?
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> There are 20 or so DFM companies. How do you segment the market and how
> many of them will you buy?
Ah, another opportunity to discuss our M&A strategy! Pass.
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> Did the technology acquired from Bindkey and implemented in ICstudio
> increase the seat sales of your full custom layout? Did Mentor get any
> increased market share as a result?
We did not acquire any technology from Bindkey.
As mentioned in the question on what other products are in the "design
to silicon" category, we're happy with the results we are getting from
our new developments in ICstation, including ICstudio.
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> Joe, what happens when your "Design using C" mantra shows flat growth
> next year... move back to System Verilog, tail between your legs?
Not sure if I'm the Joe meant by the person who asked this question, as
I'm a backend guy and think real designers use polygons.
That said, we have the best System Verilog verification on the market.
We have the best C design solution (Catapult C) on the market. Take your
pick. The idea that one design solution is going to be the holy grail
for all designers is bogus. We know it, and you know it.
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> Joe: Do fabless COT customers really need to worry about complex DFM
> (CAA/OPC/ETC) at 65nm, and do you have any real experiences (not FUD)
> to back this up?
Keep in mind that the EDA companies are playing on two sides of this
coin. We (specifically Mentor and Synopsys) are doing a lot of work on
the manufacturing side (as mentioned in the previous question this is
also where the large portion of the "DFM" revenue is coming from) to
ensure that designers don't have to worry about critical yield failures.
At the kickoff meeting for a 45 nm OPC benchmark about a year ago, our
customer spent the first part of the meeting thanking us for the work on
OPC we'd done with them for 90 nm and 65 nm. They were particularly happy
that they had not had a single OPC related critical yield failure for a
DRC clean design. This allows the foundry and the COT customer to get
more sleep.
That said, we have seen cases where doing a litho-simulation with our LFD
tool has pointed to cases where proximity effects would lower but not kill
yield. We also have a case (published with ARM) where they were able to
use our LFD tool to verify that they had done their cell designs in a way
that made them far less susceptible to context-driven parametric variation.
In neither case did either customer do a split-lot run to determine an
empirical yield improvement figure because it felt too much like hitting
yourself with a hammer to see if it hurts.
In another case we were able to demonstrate a significant yield improvement
by using production test diagnostics and a tie back to Calibre to identify
a failure mechanism in the Failure Analysis lab. The area of physical test,
both for vector generation and production diagnostics is going to be a very
potent weapon in DFM.
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