( ESNUG 461 Item 9 ) -------------------------------------------- [01/31/07]
Subject: ( ESNUG 457 #5 ) new DC-Topo correlates within 4% of Cadence FE
> Our 130 nm test design was 125 MHz with 7 clocks and 28 derived clocks.
> It had 164 IO's with 87 macros. The releases used: DC Ultra 2005.09 SP3
> (topo is only available on Ultra) & 2005.09 PhysOpt.
>
> DC with CWLM's DC with Topographical
>
> Timing Correlation 10.08% 6.02%
> Area Correlation 2.8% 1.4%
> Runtime (RTL to PG) 18.16 hr 17.7 hr
> Memory (DC+PhysOpt) 4.08 GB 4.14 GB
>
> Topo DC had better timing and area correlation compared to our manually
> created CWLM's; to our surprise it also had better area post-PhysOpt.
>
> - Jasper Lee
> Progate Group Corporation Taipei, Taiwan
From: Suneel Varma <suneel.varma=user domain=wipro not balm>
Hi, John,
I have been hearing a lot about DC Topographical lately, so I decided to try
it out in my design flow. We are quite happy with the results and we are
using it on our production design which will be taped-out mid of 2007. With
topographical we are able to speed up our production schedule by eliminating
Custom Wire-Load Model (CWLM) generation as well as significantly reduce our
instance count.
Our flow was based on CWLM's which took us 2 days to generate and needed to
be run multiple times through the chip development process. Topographical
DC allowed us to eliminate this step completely.
My testcase block that I used was about 800 K (NAND equivalent) gates and
30 macros. This block is a part of our mobile entertainment production chip
that is targeted to TSMC-90LP running at 100 Mhz. We are already XG-based,
so other than reading in the physical technology library, I had to make no
changes my scripts.
Timing Area Instances
CWLM DC 2006.06 QOR Met 855784 238551
FE post placement opt Met 893228 247205
DC-Topo 2006.06 QOR Met 737087 210118
FE post placement opt Met 764551 218275
I'm using the 6.1 release of Cadence First Encounter. DC-Topo correlated
well with it for most of the paths. Please note that we did provide to it
macro placement & floorplan co-ordinate constraints. Notice that DC-Topo
correlated within 4% of FE for both area and instances.
With DC Topographical we were able to reduce area by 14% and the instance
count by 12% compared to CWLM.
We had done further analysis on gate count reduction and found the reduction
is mainly due to auto ungroup in DC Ultra/DC-Topo.
% Change from
gate Count Instances DCT w/ Auto Ungroup
DC no WLM 813119 226780 9.9%
DC CWLM 855784 238628 15.7%
DC Ultra CWLM 784665 220461 6.1%
DC-Topo no auto ungroup 816259 229948 10.3%
DC-Topo Default 739752 207872 -
The area reduction in DC-Topo is less if we do manual/selective ungrouping
for design requirements like power domains/IP level, ECO, etc.
DC Topographical is easy and simple to use and just works out-of-the-box.
- Suneel Varma
Wipro Technologies Banglore, India
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