( ESNUG 457 Item 5 ) -------------------------------------------- [10/05/06]

Subject: ( ESNUG 456 #12 ) 3 more users eval/benchmark DC Topographical

> Our 130 nm test design was 125 MHz with 7 clocks and 28 derived clocks.
> It had 164 IO's with 87 macros.  The releases used: DC Ultra 2005.09 SP3
> (topo is only available on Ultra) & 2005.09 PhysOpt.
>
>                         DC with CWLM's       DC with Topographical
>
>     Timing Correlation     10.08%                   6.02% 
>       Area Correlation      2.8%                    1.4%
>    Runtime (RTL to PG)     18.16 hr                17.7 hr
>    Memory (DC+PhysOpt)      4.08 GB                 4.14 GB
>
> Topo DC had better timing and area correlation compared to our manually
> created CWLM's; to our surprise it also had better area post-PhysOpt.
>
>     - Jasper Lee
>       Progate Group Corporation                  Taipei, Taiwan


From: John Busco <jbusco=user domain=nvidia spot mom>

Hi John,

It's good to see posts about DC Topographical.  I've been watching and
evaluating it since last year, and am optimistic about it.

> 1) Is this 'new' Topo DC just a Synopsys marketing hocus pocus
>    repackaging of PhysOpt-into-DC?  Is Topo DC a dumbed down
>    version of PhysOpt or something actually new?

I view it as a very useful addition of PhysOpt technology into DC.  You get
all the high-level optimization of DC with a reasonable physical estimation.
(Synopsys calls it "virtual layout".)   It lets you get rid of wireload
models; think of all the extra time in the SNUG program without WLM papers!

It easily fits into your old DC synthesis flows.  Once you get the physical
libraries set up (they are already available somewhere on your site if you
use Synopsys P&R), it's just a matter of running using the compile_ultra
command and running your scripts in a new "physical" dc_shell mode.


> 2) If I mix up revs of Topo DC and PhysOpt, does my area and timing
>    correlation fall apart?

Haven't evaled this, but I'm not super-concerned because (1) I don't think
the algorithms change that dramatically between releases, (2) I don't expect
near-perfect correlation, anyway, because the floorplan assumptions will be
different between synthesis and final placement, for example.  The bar is
pretty low here: DC Topographical just has to be better than wireload models
to be useful.


> 3) How well or poorly do Topo DC generated netlists correlate with
>    Astro, Magma, and Cadence P&R flows?  If Topo DC says I've closed
>    timing with X area, will these backends later say I didn't?

I'm curious, too.  Same question applies to using other synthesis tools with
Synopsys P&R.  Cadence RTL Compiler has something called Physical Layout
Estimation (PLE), and I wonder how attractive people are finding that,
and how well it would correlate with a Synopsys back-end flow.

    - John Busco
      Nvidia                                     Santa Clara, CA

         ----    ----    ----    ----    ----    ----   ----

From Stefano Zancanaro <stefano.zancanaro=user domain=st spot mom>

Hi, John,

For us the most important thing is to have good WNS prediction from DC to
know if the netlist is ready for place and route.  Until now we have been
successfully using wireload models -- but for designs that are 130 nm and
smaller it is getting more difficult to converge with wireload models.  So
I was happy to try out DC Ultra Topographical; this is the one that does
some layout during synthesis to better correlate with post layout results.
We evaluated DC-Topo using 3 testcases and saw that the netlist generated
with topo had better structure with improvements in WNS, TNS and area.

I started this evaluation in October of 2005 and have used multiple revs of
DC/PhysOpt and ICC, but the results below are using DC 2006.06-SP1 (we got
an early access to this release from SNPS R&D) and X-2006.06 for ICC.

  Testcase 1: 500 Mhz                Area          WNS
  
               standard post-DC    3,120,365     -20 psec
             post-ICC placement    3,223,085    -330 psec
                    correlation       3.3%        15.5%

                   post-DC-Topo    3,156,630    -330 psec
             post-ICC placement    3,197,899    -190 psec
                    correlation       1.3%         7.0%

                post-CTS & opto    3,223,829    -190 psec
            post-routing & opto    3,212,906    -100 psec


  Testcase 2: 735 Mhz                Area          WNS

               standard post-DC    1,714,101    -760 psec
             post-ICC placement    2,183,553    -600 psec
                    correlation      27.4%        11.8%

                   post-DC-Topo    1,796,031    -200 psec
             post-ICC placement    1,973,322     -90 psec
                    correlation       9.8%         8.1%
 

  Testcase 3: 400 Mhz                Area          WNS

               standard post-DC    1,936,505    -150 psec
             post-ICC placement    2,219,189    -270 psec
                    correlation      14.6%         4.8%

                   post-DC-Topo    2,009,168    -100 psec
             post-ICC placement    2,019,908      -0 psec
                    correlation       0.5%         4.0%

Timing and area correlation was measured by comparing the timing and area
numbers post-synthesis and post-placement.  We verified one design using
our complete RTL to GDSII flow and the rest of the designs we verified
using synthesis in DC and placement in ICC.

Some observations:

  1. For all our testcases we saw good (under 9%) timing, area and
     power correlation with DC-T

  2. Timing improved substantially using DC-T.

  3. Minimal script changes were needed:

      - I needed to use the same command (compile_ultra) I was using in
        my standard DC synthesis flow.
      - I needed to read in my physical libraries.  I used Milkyway.
      - DC-T automatically extracted the floorplan constraints from
        the DEF when provided.

  4. We also estimated the leakage power correlation: the worst case was
     less than 18%, best case less than 5%.

We are currently incorporating DC-Topo into our production flow.

    - Stefano Zancanaro
      STMicroelectronics                         Agrate Brianza, Italy

         ----    ----    ----    ----    ----    ----   ----

From: Yang Liang <yangliang=user domain=ict.ac.cn>

Hi, John,

About a month ago I evaluated DC Topographical 2006.06, following are the
results of our evaluation showing post DC and post PhysOpt results with and
without Topographical.

We're currently working on a 90 nm design which is about 12.5 M gates.  Due
to the large amount of instances, the whole design is divided into several
physical design modules.  One of the major issues we face with our current
flow is that the inconsistency between DC and PhysOpt requires us to go back
and forth between DC and PhysOpt to close timing.  Because of the inaccurate
prediction in wire delay using WLM, some of our critical paths weren't being
optimized in DC -- creating timing closure problems.  Realizing that topo
could be an ideal solution, I decided to see for myself if its marketing
pitch was just vaporware or had some truth to it.  

I ran topographical on 6 physical design modules using the same timing, area
and power constraints for synthesis and placement.  We also read in relative
port locations in DC as well.  (Yes, DC reads in some physical constraints.)

With the topo flow we found that the right critical paths were identified
and optimized in DC.  After a few modifications to our physical constraints
that were being provided to DC most modules achieve the desired area, timing
and power.  Take a look at the module 3 results for example, the timing is
0.90 nsec in DC-Topo compared with 0.85 nsec in PhysOpt, the area is
903222 um^2 in DC-Topo compared with 885334 um^2 in PhysOpt, and so on.
Their virtual layout based synthesis is really amazing!! 

Timing (nsec)
                PhysOpt    DC    delta    PhysOpt  DC-Topo   delta
    module 1     0.79     0.68   11.0%      0.76    0.80      4.0%
    module 2     0.83     0.71   12.0%      0.84    0.91      7.0%
    module 3     0.85     0.75   10.0%      0.85    0.90      5.0%
    module 4     1.09     0.77   32.0%      0.90    1.08     18.0%
    module 5     0.80     0.74    6.0%      0.77    1.00     23.0%
    module 6     0.80     0.73    7.0%      0.79    0.87      8.0%


Area (um^2)
                PhysOpt    DC    delta    PhysOpt  DC-Topo   delta
    module 1    555810   459896  17.3%     518749   518018    0.1%
    module 2   1986818  1794151   9.7%    1824914  1807397    1.0%
    module 3    895797   802599  10.4%     885334   903222    2.0%
    module 4   2546219  2189640  14.0%    2486907  2536705    2.0%
    module 5   1098973   836429  23.9%    1091212  1105160    1.3%
    module 6   8253125  8020965   2.8%     832668  8310830    0.2%

Note: The plain vanilla DC runs above used wireload models and then PhysOpt
was run on its generated netlist.  The DC-Topo runs did not use wireload
models (of course) and then its output was fed into PhysOpt.

I did find that topo can be a little pessimistic with its predictions with
designs that have lots of predefined RAM blocks.  For example with module 4
(memory block) the timing is 1.08 nsec in DC-Topo compared to 0.90 nsec in
PhysOpt.  It's also worth noting when we provided port coordinates to DC,
for some of the modules the topographical result were very pessimistic.
In the worst case module showed an increase of 30%. 

Overall though, DC-Topo shows very good timing, area and power prediction
to PhysOpt results.  I believe this technology will be key in solving our
timing closure problems, especially for deep sub-micron technology at 90 nm
and below.  We are currently in the process of integrating DC topographical
into our production flow.

    - Yang Liang
      Chinese Academy of Sciences                Beijing, China
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