( ESNUG 457 Item 1 ) -------------------------------------------- [10/05/06]
Subject: To balance out the Apache love fest; a detailed Sequence review
> Editor's Note: A few months ago I sent out a questionaire specifically
> aimed at users rating the Apache tools, Apache support, and the Apache
> company culture overall. Here's what 38 Apache customers reported.
>
> - from http://www.deepchip.com/posts/0455.html
From: [ Inspector Clouseau ]
Hi, John,
Please keep me anonymous.
After seeing ESNUG 455, I felt you needed an eval of Sequence's tools to
balance out that Apache love fest. I started working closely with Sequence
a few years ago and use Sequence CoolTime for dynamic voltage drop, leakage
power, timing, SI, and electro-migration analysis.
The CoolTime things I liked best:
a. Capacity. I have never run into capacity limits for CoolTime. Sequence
claims a 10 M gate capacity, and I ran a 10+ M gate chip through it
easily when I hit the capacity limits at the block level using Synopsys
PrimeRail. CoolTime currently analyzes up to 16 separate rails at the
same time; Synopsys PrimeRail cannot analyze 2 rails simultaneously due
to capacity issues. To get the worse case voltage across the gate, you
need an absolute minimum of two rails, because to know the speed of a
gate at any time, you must know the effective voltage encompassing both
VDD drop and VSS bounce. PrimeRail can't do this!
b. Accuracy. CoolTime claimed accuracy to within 3% of HSPICE, which I
did not believe was possible until I saw the CCF (Current Configuration
Format) models for each of the leaf cells. The Elmo characterization
tool is built into CoolTime. It worked the first time I used it, and
after only 2hours it generated the CCF files for 600 cells. In the
CCF file, current is captured for both VDD and VSS for each timing arch
in the existing .lib. CCF currents are then applied to the physical
power rails connected to each gate and accumulated based on actual
VCD/fsdb activity and rail resistance. The CCF format also provides a
highly accurate derating based on worst case effective voltage.
CoolTime's analysis engine iterates 3 times based on the actual voltage
drop before reporting a worst case effective voltage of a given gate
instance. (No other commercial power analysis tool iterates -- it's
like is telling someone their gas tank is 80% full when it is really
only 60% full.) With each iteration, CoolTime is able to use the
voltage from before instead of just stupidly using ideal voltage. The
result is you can more accurately determine the worst case effective
voltage. The worst case effective voltage is then used to apply a
more realistic current to the grid.
When you run PrimeRail, you can only analyze one rail at a time, which
is not the complete picture; additionally, PrimeRail only uses ideal
rails, meaning ideal currents and voltages for every gate and every
device. For 3 years Sequence is still the only one doing this, and no
one else is close.
c. Speed. Here's a runtime benchmark of CoolTime on 2 designs on a
2.4 GHz, 16 GB, single CPU Opteron:
instances 2M 300K
SPEF nodes 10+ M 5+ M
sim length 8 nsec 5 nsec
mem use 7.4 GB 4.0 GB
wall clock 3.5 hrs 16 min - *
The 8 nsec is how long the activity runs for. For P&R, I select the
activity start and end using PowerTheater. The start and end time
corresponds to a window of time where the highest dynamic voltage drop
can be observed. There may be many of these windows per power vector
or it may be only one that is characteristic of many cycles that look
the same. For the large analysis, I chose 8 nsec as representative of
the highest activity and for the smaller block I chose 5 nsec. In the
large case, I used 400 psec time steps where in the smaller block level
case I used 50 psec time steps.
CoolTime averages the power consumption per instance for each time step
and shows the Power Current, Power Voltage, Ground Current and Ground
Voltage in movie mode all in the same display. If a more detailed view
is needed, go to the time step of interest and bring up the detailed
viewer. Either of the four windows can be chosen or simply view
colorization based on worst case effective voltage. In this view, the
actual power rails can be colorized based on voltage drop or simply
overlayed on top of the instance colorization.
* - See the "Memo" section at the bottom of this letter for this time.
d. Sequence didn't have full custom annotation and analysis a few years
ago, but they were flexible and nimble enough to add this to their
cell-based product when I requested it.
e. Built-in Extraction. Sequence's Columbus is a stand alone product,
which recently has also become an option for CoolTime. It extracts
tremendously optimized or highly accurate SPEFs directly from GDS for
all macro and leaf cell power rails. Signals can also be extracted
for signal based EM analysis.
f. Hierarchical DEF support. All SoC designs have multiple levels of
hierarchy, and take advantage of fully hardened place and route,
reusable macros. CoolTime stands alone as the only power analysis
tool today supporting unlimited levels of hierarchical DEF.
g. Tcl based. This stems from their rich Tcl support in PowerTheater.
h. Ability to feed optimization ECOs back into our Synopsys Astro flow.
i. Ability to produce timing results that agree with PrimeTime-SI.
Sequence's ECOs plug and play flawlessly into our design flow, and
consistently produce expected/predicted results.
j. Concurrent timing, SI and power analysis. CoolTime's timing engine is
part of the power analysis, so we can immediately see the improvement
to the timing with any improvement we make to the power grid. We take
this timing result and feed it back in as an ECO to Astro for a better
placement that meets both timing and dynamic power constraints. This
is the progression we follow:
- Use dynamic power analysis to improve power grid. For example,
where ever there is a red spot we add a power connection,
resulting in an imbalanced grid.
- Get the timing report, get an ECO, bring it back into CoolTime.
k. Power Optimization. You can run optimization to improve timing based
on dynamic power analysis results, adding decoupling caps very close to
the heaviest dynamic activity. This results in a 3 to 5% leakage
improvement. CoolTime intelligently spreads the cells and inserts
decoupling caps. At lower geometries all transistors leak, so you
only want the decoupling caps that benefit your dynamic performance.
After doing the optimization, CoolTime can write the ECO to send back
to Synopsys Astro.
l. Ease of use. Sequence has created numerous scripts and checkers to
make first-time execution of power analysis flows easier.
The things that CoolTime could do better:
a. Course grain MTCMOS analysis. Power gating is rapidly becoming the
main theme for achieving low power at sub-90 nm. CoolTime has the
capability to automatically insert fine grain switch cells into your
design while managing the routing of the extra rail. The analysis
of this "turn-on" and "full-on" state of the switch is critical
considering that there is logic nearby that never powered off.
CoolTime needs both fine grain and coarse grain analysis overlapping
into a new capability.
b. CoolTime needs a tighter integration of its custom power analysis with
PowerTheater. Many of the power analysis features in PowerTheater
would also be nice in the full custom world. The family tree showing
power consumption per level of hierarchy by colorization and also the
waveform analyzer providing assistance in defining start/stop times
for power events would both be useful to custom power analysis.
c. More features for custom analysis: it needs voltage isolation cells
and level shifters checks within custom blocks. When custom blocks
have more than one power domain, the proper protocol between domains
must still be verified. Histograms showing resistance to custom cells
instantiated inside custom blocks would be nice.
Below are some of the more noteworthy items Sequence has added recently.
CoolCheck -- formal grid verification. CoolCheck is amazing. It uses the
same setup as CoolTime SoC to rapidly generate a histogram of the minimum
resistance from a source pin/pad to each instance. We completed a formal
grid analysis for a 300K design in under 5 minutes, letting us highlight
the worst paths in the fast layout viewer, and quickly decide whether or
not to improve the grid.
CoolCheck uses the sum of the SPEF resistors to determine the minimum
resistance path in the histogram (it doesn't use current). It's extremely
useful in gaining an early look at the electrical aspects of the design
and measuring the over all quality of the grid. High resistance paths
naturally bubble to the top of the list of paths (the tail of the histogram)
so we can improve the grid to reduce the tail and push all values to a
specified minimum value.
Multiple Format and Overlay Viewer -- The viewer they use is the same for
all the CoolProducts (e.g. CoolTime, CoolCheck, CoolPower.) This viewer
is the fastest layout viewer I have seen. I was able to read in a 2 GB
GDS in less than 1 minute!
We are very visually oriented in the power analysis world. A trained eye
can easily spot a problem with a power grid. With only one glance, we all
recognize that straight lines are bad, close color contour boundaries are
bad, and maximum dynamic drop over a specified limit is bad. The Sequence
viewer lets you view a colorized layout with the voltage drop, where you
can highlight the actual critical timing path. It rapidly displays the
contours for not just place and route regions but also custom annotated
regions. Other power overlay viewers such as PrimeRail are often incapable
of showing you the source data, e.g. the GDS view, LEF view, DEF view or
just the Power and Ground rails. All of these views are available in the
Sequence viewer and very helpful in identifying problems with incoming data.
Power Analysis includes Memories -- Most of the time, the memory portion
of your design is literally pushed to the side to maximize space for the
P&R region. Not that memories aren't important, but their ports can
easily be located on only one side. The result is you have a P&R region
that must receive power via conduction through the memory and it is
therefore affected by the consumption of the memory.
Power analysis cannot be considered complete when the memory instance is
all the same color, and CoolTime is the only power analysis product capable
of modeling multi-rail dynamic memory consumption and conduction at the
same time. For years, Cadence/Apache/Synopsys has been claiming to do
dynamic power analysis while ignoring the important power consumption of
and conduction through memories. Synopsys PrimeRail, Cadence VoltageStorm,
and Apache can't do this.
Such analysis requires a simulation result from a high capacity simulator
(like HSIM) feeding into each annotated memory. With CoolTime, for the
first time, I am able to see full dynamic power annotation that incorporates
the memories. To maximize the accuracy, the designer:
- Identifies each memory transaction type by a particular signal or
combination of signals (the trigger).
- Simulates in HSIM (without rails), capturing one current waveform
per level of hierarchy, and being careful not dump the array nodes.
The majority of power is consumed by circuits other than the bitcell array
area, thus consumption currents for the bitcell array can be ignored while
conduction through the array area is not ignored. The HSIM results can be
thought of as "ideal", since actual rails were not in the simulation. The
"trigger" is then used as the enable for these ideal currents to be
annotated over local "regions" into a fully extracted SPEF using a built-in
CoolTime capability called "Memo".
Memo -- This 16 min timing covered in part "c" of this letter involved a
more detailed extraction for highly accurate Electro-migration with 7 memory
regions annotated. Memo is a new capability that can be used to annotate
currents onto custom memories. These currents are then calculated along
with conduction to indicate the actual dynamic IR drop. In the case of the
16 min smaller block level example, I found that 95% of the power was being
consumed by 7 rectangular areas within the memory. Using Memo annotation it
is quite easy to annotate one of 256 or the average across the entire array
of 256 cells. The designer choses the level of metal, via, or combination
to be annotated. These 7 regions equated to about 50K SPEF ports at METAL1.
The actual current from HSIM for these 7 regions based on an actual boolean
trigger contribute in real time to the over all dynamic voltage drop. All
of the power rails are measured and qualified based on actual consumption.
The memories are no longer ignored.
More detailed extraction:
In order to reduce the extraction to just what is needed for dynamic power
analysis, the VIA resistance is combined w/ power & ground rail resistance
as one resistor. The data is dramatically reduced and the analysis runs
much faster without any loss of accuracy. In the case of Electro-migration
analysis, the VIAs cannot be ignored because they may actually be the cause
of a violation. Therefore, the extraction is much more detailed and run
times are (in my experience) about 30% longer.
- [ Inspector Clouseau ]
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