( ESNUG 456 Item 13 ) ------------------------------------------- [07/17/06]
From: Sam Bishai <sbishai=user domain=cisco spot calm>
Subject: DC 2006.06 area benchmarks; customer dumps PhysOpt for Topo DC
Hi John,
We're getting ready to start a very demanding 65 nm project and I got the
chance to test some preliminary subcircuits we have using a beta version of
DC 2006.06. While timing is important to us, my main concern was the area
numbers in order to fit in a specified die size.
Design-A No LVT Cells Enabled LVT Cells Enabled
DC 2005.09 2006.06 2005.09 2006.06
MHz 375 375 375 375
logic_levels 26 26 23 26
Levels 23 23 11 13
wns -0.17 -0.22 0 0
tns -6.48 -9.32 0 0
violating # 49 48 0 0
comb 1042810 1026677 1046121 1027420
noncomb 1373329 1374067 1373295 1374139
total area 2416551 2400414 2419871 2401227
Area Improv % 1% 1%
Design-B No LVT Cells Enabled LVT Cells Enabled
DC 2005.09 2006.06 2005.09 2006.06
MHz 250(300) 250(300) 250(300) 250(300)
logic_levels 39 37 38 37
Levels 36 32 28 25
wns -0.26 -0.03 0 0
tns -186.42 -10.39 0 0
violating # 768 677 0 0
comb 395801 286983 353308 265083
noncomb 26915 26488 26659 26477
total area 422713 313392 379992 291570
Area Improv % 25% 23%
Although DC 2006.6 improved the area in all cases, I couldn't close timing
until I had the low voltage cells enabled.
Design-C DC 2005.09 2006.06
MHz 540 540
logic_levels 19 18
Levels 16 16
wns 0 0
tns 0 0
violating # 0 0
comb 14531 12784
noncomb 5107 5221
total area 19639 18005
Area Improv % 8%
Design-D DC 2005.09 2006.06
MHz 300 300
logic_levels 23 25
Levels 4 5
wns 0 0
tns 0 0
violating # 0 0
comb 12400 12175
noncomb 891 891
total area 13291 13066
Area Improv % 2%
Design-E DC 2005.09 2006.06
MHz 270 270
logic_levels 34 33
Levels 26 11
wns 0 0
tns 0 0
violating # 0 0
comb 119297 98323
noncomb 318904 318790
total area 438212 417114
Area Improv % 5%
All circuits I tested produced better area in the DC 2006.06 beta version
than with DC 2005.09-SP3. I saw area improvement as little as 1% to as high
as 25% -- with the average area improvement being around 9%. The area
savings were more obvious in combinational circuits using complex MUXing and
XORing. I attribute this improvement to the library-aware mapping and
structuring build in the new algorithms.
Although I did not measure runtimes and memory capacity due to changes in
machines and loads during my testing all my runs in 2006.06 were executed
faster than the 2005.09. I saw it handle 350K instances with no problems.
I did manage to run a couple of blocks using topographical synthesis and I
noticed the results obtained were within 2% of PhysOpt placement results.
In a complex MUXing experiment I started with DC 2005.09-SP3 and then ran
PhysOpt. I did the same using topographical synthesis and PhysOpt and I got
a savings of 3.4% in area with it. Due to project demands I did not have
the time to do more DC topo testing.
In the new 65 nm project we intend to move all synthesis to v 2006.06 once
it is officially released. Its savings in area and its better handling of
complex combinational circuitry is important for our designs. We also plan
to use Topographical DC. In some cases we might bypass PhysOpt and hand off
the topographical generated netlist straight to layout. (Note: our fab uses
his own physical synthesis tool and not IC Compiler).
- Sam Bishai
Cisco Systems Kanata, ON, Canada
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