( ESNUG 455 Item 2 ) -------------------------------------------- [06/29/06]
Subject: Users on the Apache RedHawk PowerGate option
NEW & IFFY -- The vast majority of respondants to my survey either didn't
know of or didn't use RedHawk's PowerGate. It's not hated or anything like
that; most users are just at the tire-kicking stage with it.
"Do you use RedHawk's PowerGate option for low power? How did it work?"
We used PowerGate to do full-chip low power ramp-up analysis for our
multimedia application processor. The chip used a 90 nm process, and
had 2.3 million nets switching at 133 MHz, for 1.7 million placeable
instances, including 5 hard macros and 80 millions transistors. It
has been now manufactured and is fully functional.
We created 2 power domains which are activated using embedded power
switches... they are header switches and are located in the IO-ring.
-Sub-system shuts down when not in use
-Software controlled dynamic switch on & off depending on
sub-system state
To reduce power to a minimum, we used:
- optimal HW/SW partitioning
- power switches to disable most of the chip
- high-VT process to reduce leakage--switching on & off sub systems
- via intrinsic low power sub systems
Those power switches made our full-chip power grid verification more
difficult -- they were the link between the 2 power domains, and
contributed to the voltage drop degradation. Our verification
methodology was:
1) Static Analysis. As soon as we had an initial placement & the power
grid routed, we used RedHawk to do static analysis to find the gross
errors on the power grid. For example, at the floorplanning stage we
were able to identify a missing hard-block connection, where we were
able to isolate Vdd-Gnd shorts. This was very easy and very early
when compared to our usual approach, which was to LVC Calibre at the
late stages of the design.
2) Dynamic Analysis. Once we had a detailed placement w/ a synthesized
clock-tree, we used RedHawk to do vectorless dynamic analysis to find
more issues on the power grid based on simultaneous-switching events.
We also validated power pad number and distribution.
3) Ramp-up Simulation. When our chip was routed and had met timing
closure, we used PowerGate to do a ramp-up and dynamic analysis based
on the VCD. We computed the ramp-up time and verified the ramp-up
effect on already ON cells. We also computed the sign-off worst Vdd
drop and ground bounce values. We assessed how many switches were
required and limited the peak current during ramp-up. We also used
the ramp-up results to improve the logic enabling the power switches.
For our ramp-up analysis, PowerGate characterized the standard cells as
a non-linear capacitance over the whole voltage range, and automatically
simulated the switch in SPICE to create a model. Memories were simply
represented by a LEF and a lib. Our main goal for using PowerGate was
to better understand the switches and the chip behavior during the
ramp-up.
1) PowerGate's Movie Mode. "Movie Mode" showed a movie of what was
going on as the switches turned on and off during the ramp-up. We
could see everything starting from the pads, including that the power
was progressing smoothly toward the center of the chip. The color
waves are in 100 mV increments. The movie let us visually check for
power propagation irregularities, and the impact from the 'always-on'
cells. We only simulated the chip when the switches were turned ON,
and not when they were turned OFF.
We then further analyzed the irregularities we saw in the ramp-up
movie by selecting several instances throughout the chip and viewing
the Vdd node for each of them. By doing this, we identified the
unbalanced areas during the ramp-up. In one instance we spotted an
area where the ramp-up was too slow. We also used the Vdd waveforms
to check the impact of the ramp-up on cells in the 'always-on' area.
2) Peak Current Analysis. We were also concerned about the switches'
power pad current consumption. We adjusted the peak current by
defining the ideal number of power switches to avoid current
saturation. We also viewed the total peak current in the chip
during ramp-up and adjusted it by defining the switches' ideal
turn-on sequence, e.g. simultaneous turn-ons, or turn-ons with a
100 or 200 ps interval between switches.
3) Vdd oscillations. Since we could also look at how the Vdd node
depended on the switch turn-on sequence, we could adjust Vdd
oscillations during ramp-up by defining the right number of power
switches and the delay in turning on each power switch. We combined
this analysis with the peak current analysis to determine the best
ramp-up sequence to limit the peak current and to avoid Vdd
oscillations during ramp-up.
Apache recently improved PowerGate by making the instance's Vdd waveform
directly accessible from the PowerGate/RedHawk environment; in the past
we had to extract them from several files. But we can only view only
one curve at a time -- we would prefer to view several Vdd curves on the
same graph. Additionally, some board components like the package's
current limitation are tough to model in the ramp-up setup.
PowerGate was easy to set-up and use, and the movie mode made it easy to
visualize how the circuit was behaving. Apache is the only vendor to
provide full-chip transient simulation.
I should point out that none of our runs lasted more than overnight.
- Ludovic Fievet of STmicroelectronics
No.
- [ An Anon Engineer ]
The Power gate option is good and works well for in rush current
analysis, and analyzing effects of IR on the rest of the chip if
different powering schemes are used.
- [ An Anon Engineer ]
We did not test PowerGate but from the demos it looks like a useful
feature The only other vendor that has it is Sequence CoolTime.
- [ An Anon Engineer ]
No
- [ An Anon Engineer ]
No
- [ An Anon Engineer ]
Not yet for both.
- [ An Anon Engineer ]
So far, I have only used the PowerGate ramp-up analysis on a fairly
small 50K gate block, which has since been completed.
We're using power switches in our design, retention flops all that kind
of stuff. It's been pretty tough characterising these cells.
PowerGate's 'movie-mode' shows the layout and how the voltages change
as switches turn on and off. It is very flashy in a presentation, but
it was tricky to extract information from it. For example making sure
that the voltage between two instances connected together is within the
expected margin. Additionally, we did have some design flow issues.
The tool worked fairly well on a simple design, for example, standard
cells and switches. But since I have only tested it on a small design,
I cannot comment on how well it works on a more complex designs with
switched sub-blocks, memories, and multiple power domains... it may
take a lot longer to set up.
- [ An Anon Engineer ]
I didn't use, or even don't know the PowerGate nor FAO. We are just
running static and dynamic IR drop and electromigration analysis, no
backannotation on signal delay.
- [ An Anon Engineer ]
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