( ESNUG 454 Item 18 ) ------------------------------------------- [04/28/06]
Subject: ( ESNUG 451 #7 ) Two more Users yarping about EVE ZeBu emulation
> I had a constrained random testbench that ran on ZeBu for weeks, and it
> caught cases which were not tested by our Verilog test-environment,
> enabling us to fix the bugs prior to sign-off. I have had a great overall
> experience using ZeBu and would recommended it.
>
> - Rakesh Mehta
> LTX Corp. San Jose, CA
From: Mike Dickman <mpd=user domain=pasemi spot gone>
Hi, John,
My colleague, Tse-Yu Yeh, and I extensively evaluated several emulators and
eventually purchased our first ZeBu-XL box a year ago. Our criteria included
capacity, speed, pricing, ease of use, and to some degree, debug capability.
We had small portions of our design up and running in ZeBu within a couple
of weeks. Within a month or two, we had successfully mapped a large chunk of
the design into the emulator.
Our largest emulation model utilizes 32 FPGAs or 24 million gates including
standard logic and SRAMs. This maxes out our ZeBu-XL's capacity. We stubbed
out some portions of our design to fit into the box.
Several of our designs run with a ZeBu-XL internal clock speed of 1 MHz or
more. That speed drops into the 800 KHz range when significant amounts of
data are transfered between the emulation box and an attached PC. At these
speeds, we are seeing a speedup of 5,000X over SW simulation.
We use ZeBu-XL in transactor-based emulation mode where it is connected to
software transactors as opposed to real hardware devices. Our emulation
setup mirrors our simulation environment, allowing us to drastically
accelerate all of our simulation runs. We also use the same environment
to boot operating systems, run applications, and connect to real devices
through software bridges; instead of plugging into the hardware, we
plug into transactors.
ZeBu-XL's compilation flow is pretty reasonable. It has an automatic
partitioner, but in practice, the design speeds produced with that tool are
a little slow. To get the best results from emulation, we hand partition our
designs. The partitioning process takes some effort, but isn't as bad as one
might think. Partitioning a big design that uses all 32 FPGAs (24 M gates)
takes a day or two at 750 K gates per FPGA. Smaller designs are much easier
to partition; if the box is lightly used, you can partition a design in 30
minutes. It's not until the box begins to fill up that it gets to be more
difficult. We hand partition our designs for speed. Although ZeBu can do
it automatically, it produces a final design that is much slower.
Once the partition is created, it can be used for the life of the design
with a little maintenance. The ZeBu system is FPGA based, so FPGA place and
route issues can pop up from time to time, especially if the design is
pushing the capacity of the system.
Loading an existing model into the Zebu box takes 5 minutes. Building a
32 FPGA model takes about 10 hours, 4 hours for synthesis, 4 hours for FPGA
place and route, and 2 hours for the Zebu tools (logic insertion, partition
and final merge). A 16 FPGA design might take 6 hours.
ZeBu's debug approach uses the FPGAs internal scan mechanism. This allows us
to dump out the values of all state elements. We use the Novas Siloti tool
to map this gate level dump into RTL-level signals and to inflate the data
so that we can examine the intermediate nodes of the design. When a fix is
made, you can reduce the number of steps required to build a model.
Depending on where it is, it will take between 3 and 7 hours to fix a model.
If you can fix it in the transactor, it will only take 30 minutes to rebuild
the model.
We are very happy with the internal clock speeds provided by ZeBu. Small
designs run much faster than big designs, as it all depends on the number of
interconnects between FPGAs. We are getting around 1 MHz on medium sized
models (20 FPGAs).
In addition, the transactor ease-of-use and speed have allowed us to do
things in emulation that we have been unable to do in the past. Software
transactors have proven to be much more flexible than connections directly
to hardware or to hardware speed gaskets.
P.A. Semi designs a family of 64-bit multicore processors featuring a
system-on-chip architecture with all northbridge, southbridge, and
network-interface functionality integrated into a single-chip. Emulation is
almost a requirement for testing chips of this size and complexity. We have
used it to catch hundreds of bugs in just days instead of the months or
years it may have taken in simulation. We have also captured several bugs
while running real world OS's and applications. Without emulation, it's
likely that many of these problems would have made it into silicon. We
recommend Eve's ZeBu platform to any engineer who could benefit from a
substantial increase in simulation throughput.
- Mike Dickman
Palo Alto Semiconductor Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: [ Less Filling, Tastes Great ]
Hi, John,
Please keep me anonymous
We looked into several high capacity emulators/accelerators including EVE
ZeBu-XL, Cadence Palladium, Mentor VStation, Axis, Tharas, Aptix, and very
briefly at ProDesign.
Our main decision criterion was price for performance, but we also needed
something that wasn't prohibitively expensive for very large designs
(around 40 M gates). We wanted to be able to run around 5 trillion cycles
worth of validation for 3 months before tape-out, but we weren't willing
to spend millions for it. In the end, we selected EVE's ZeBu-XL based on
its having the best performance at the lowest cost. We began production
use of ZeBu-XL in 2005.
As for results, for a 20 M gate design we saw a raw speed just of around
400 KHz with ZeBu-XL. This may seem low compared to the multi-MHz speeds
others are used to seeing with ZeBu-XL, but because our design was large,
we spread it across multiple FPGAs, and the number of inter-FPGA connections
was larger than a typical SoC design made up of smaller components. We also
had thousands of multi-ported memory arrays that needed to be time sliced.
This 400 KHz we see with ZeBu is about 10X higher performance of the speed
we saw for the same design on a Palladium.
We currently primarily use ZeBu in simulation acceleration mode where we
connect it to an internal validation environment with C/C++ and Perl
components. We are also working to develop transactors for high-speed
interaction between our checkers and the emulation model. We judiciously
use both the static and dynamic probing capabilities of ZeBu-XL depending on
the need: dynamic probing allows full state visibility but at low speeds, so
it is great for debug and/or infrequent signal access; we use static probing
for those signals we access frequently -- these need to be identified at
compile-time. These trade-offs are similar to those in other emulators like
Palladium and VStation.
We really like EVE's "reconfigurable testbench" capability. This allows us
to decouple our transactors from the DUT, allowing the DUT to be built and
run separately as needed. EVE seems to have done a great job when it comes
to transaction-based interfacing -- their system was designed for it from
the ground up, and in fact, their C/C++ signal-level API is actually a
transactor itself.
ZeBu-XL shortcomings:
Compared to the comprehensive emulator lines from Cadence and Mentor, ZeBu-XL
is a bit lacking on the compile side. Since the Zebu-XL system is based on
Xilinx FPGAs, Xilinx tools must used for final P&R. However, the choice of
synthesis/mapping tool is left to the user. This aspect of the compile
process is a downside for EVE compared with other full-service emulators.
(ZeBu is probably a step up from the FPGA prototyping world, but won't work
well for cases like ours with large designs, lots of memories, etc. However,
we know that EVE is working on filling out its compile flow, and we look
forward to that.)
On the execution/debug side, ZeBu-XL is not as advanced in its in-circuit
emulation (ICE) debug capabilities as Palladium or VStation. This is partly
because EVE focuses on the transactor side, but ideally there would be one
product that does both simulation acceleration and ICE extremely well.
We just started production use of ZeBu-XL in late 2005 for some legacy use
models, and we're already enjoying a significant increase in cycle bandwidth
with it. In 2006, we plan to run tens of trillions of pre-Si validation
cycles on ZeBu-XLs (inexpensive enough for us to buy multiple), which is
something that we considered cost-prohibitive in the past.
The bottom line is that we found ZeBu-XL to provide us the most cycles for
our dollar, and I would definitely recommend it to others.
- [ Less Filling, Tastes Great ]
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