( ESNUG 454 Item 12 ) ------------------------------------------- [04/28/06]
From: [ Obelix of Armorica ]
Subject: Gradient FireBolt's temperatures correlate well with test chip
Hi, John,
Please keep me anonymous.
I know you like user reviews of new EDA tools, so I thought I'd share
with you our first cut at evaluating Gradient FireBolt. Our first
question about Gradient was whether or not it predicted real life
thermal behavior of a chip, so we used a test chip used to validate
the tool for package temperature analysis.
actual Tj (C) FireBolt Tj (C)
Power JA measured average diode
Package (W) (K/W) using diode temperature
--------- ----- ----- ----------- -----------
Epad1 2.19 29.7 87 87.91
Epad2 2.18 29.4 86 86.97
Slug1 2.13 28.2 82 82.96
Slug2 2.12 27.8 81 81.88
Personally, I think this is a good indication of accuracy but a more
detailed investigation must be made. We are currently considering
how to investigate a test chip dedicated to our unusually high voltage
and high current designs.
We started to work with Gradient before FireBolt was actually released.
Gradient is able to accept Open Access, LEF/DEF, SDF, DSPF (these last two
were not used in our evaluation) so its thermal analysis fit into our
mostly Cadence flow along with our Mentor (Eldo and Calibre) and Synopsys
(Star-RCX and Nanosim) tools. The only information that was harder to
obtain is the package model -- because it was an internal package, we were
missing some data.
The things that impact temperature the most are power density distribution
and self-heating in SOI processes. Following this are probably IR drop and
electromigration, with packaging also having some impact.
We tested Gradient using different approaches: floorplanning, transistor
level, full chip mixed flow (some instances LEF/DEF, some transistor level);
the tool proved to be flexible enough to work at these different design
phases. Definitely the more detail we had, the more accurate the Gradient
results appeared to be.
My one concern in using Gradient tool is with the package description. The
package contribution is really important, but sometimes it is difficult for
us to obtain the right data for the tool. Other tools are required to
create this input data. For example, full chip SPICE simulation is needed
to be able to perform dynamic analysis at transistor level. At the time of
our comparision, we were not able to use Nanosim, our golden simulator, to
produce the needed data, due to a Nanosim problem. So what we did was to
reduce the transistor level part to analyze and used Eldo to obtain the
necessary input data.
- [ Obelix of Armorica ]
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