( ESNUG 454 Item 6 ) -------------------------------------------- [04/28/06]
From: Robert Knoth <robert.j.knoth=user domain=exgate.tek spot gone>
Subject: One user's first hand eval of RioMagic chip/package co-design tool
Hi John,
I have been using RioMagic, the chip/package co-design tool from startup
Rio Design Automation. Their tool helps close the loop between the chip
design and package design.
All of our IC package designs at Tektronix use a combination of our internal
polygon editor called "icedit", Excel spreadsheets, and a lot of emails.
Once we hand off our package info to a 3rd party for design, an endless
stream of iterations and missed intentions results.
Through our involvement with Magma, I started working with the people at
Rio. They have a tool which helps connect the ASIC floorplanning process
with package design and the PCB. It is able to take information via
LEF/DEF, or (as in our case) Magma Volcano.
In the tool, multiple package designs can be rapidly explored and tested.
It uses a rough SI analysis and a cost function for signal quality to
create signal-power-ground ratios. (There is no need for HFSS-like accuracy
when first exploring a design.) Groups of signals can be specified for
delay matching or placement considerations.
The beauty is how RioMagic fits into the whole design flow. Instead of a
set of Excel files and sketches, we are able to hand off a Cadence APD file
with global routes to our package designers. Very little room for confusion
and misunderstandings is left.
I tested Rio on a design which I had taped out a few months prior. It was
a small ASIC with a large number of custom macros and two DDR interfaces.
Due to a time crunch then, I did not have time to experiment with multiple
IO placements, and settled on a very simple pad ring which resulted in a
larger die area in the original design. When I revisited that design with
RioMagic, I was able to quickly explore a concentric pad ring design that
shrunk the die area by 24%!
I presented a paper on this design at the last Magma User Conference with
Helene Deng of Rio.
The Rio tool is fairly mature, but does have some room to grow. A few of
my observations from the testcase I ran:
1. There is a lack of automation for area I/O blocks bump layout
assignment and routing. While RioMagic does placement and
routing of I/O pad rings, however your cover macros need to be
created via TCL scripts. Some level of automation plus basic
layout editing capability can make this job a lot easier.
2. True diff pair routing is not fully supported for area I/O. At
the time of my eval, the differential pair routing rules were
not supported if the diff pairs belong to the area I/O blocks such
as SerDes blocks. (This has supposedly been fixed in the latest
release although I haven't a chance to try it out.) I also
encountered a few problems in routing although fixes were quickly
provided.
3. Stability issues. There were a few crashes, some are due to
incomplete data. The tool should do a better job at checking
and reporting data errors.
4. RioMagic needs better integration with chip analysis tools. The
tool focuses on the I/O power estimation and analysis. But since
it has both the chip and package data, it should be better
integrated with the chip analysis tool (ie. BlastRail) by feeding
it a more accurate package environment.
It's rare that an EDA company understands the tradeoff between speed and
accuracy. Rio has done this very well. Their prototyping approach to
package/chip design works.
- Rob Knoth
Tektronix Beaverton, OR
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