( ESNUG 454 Item 5 ) -------------------------------------------- [04/28/06]
Subject: ( ESNUG 451 #5 ) Well, we just renewed our JasperGold licenses
> Lost in these rumors are the really good things happening at Jasper. For
> the record: We continue to acquire new customer logos, including a major
> win at a large European consumer company where we displaced Cadence IFV.
> We received renewal and expansion orders from existing customers in the US
> and Japan, and now have several $1M+ customers. We have helped customers
> propagate formal verification to multiple users on projects at multiple
> sites. Our products are consistently winning technical evals. Finally,
> we have a good cash position and are NOT currently fund-raising.
>
> - Kathryn Kranen, CEO
> Jasper DA Mountain View, CA
From: Homayoon Akhiani <hakhiani=user domain=azulsystems spot gone>
Hi John,
Here at Azul, we have been a Jasper customer for the past 2 and half year.
The tool was mostly used on specific areas of the processor design where
traditional SW simulation was weak.
Late last year, we decided to run a re-eval of Jasper's tools. I thought
your readers might be interested in knowing what we have found.
As part of our design, we had a large data switching network (around 1.5
million gates) that we wanted to verify. The logic was fairly complicated
and we felt formal would be a good fit for proving the 5 properties we had
for the code. Most of the properties were end-to-end functional checks and
not very localized. Many of the early checks completely verified with very
little effort (few minute run time.) Jasper tunneling technology showed
that about 10% of the design to be needed for each proof. Later we got
more sophisticated and bumped it up to 14 complex properties; some of which
took overnight runs in Jasper. This required us to use Jasper's internal
datapath models (PPMs) in addition.
Using standard SW simulation we found 100's of bugs in our chip. The Jasper
approach found 4 bugs, but they were really ugly subtle bugs. One of them
had to do with a timeout error register which was not being reset properly.
It needed 2^32 cycles to pass to see the failure in simulation. But with
Jasper, I hit the case in couple of minutes. After bug analysis, we found
that 3 of them would have never been hit by focus or random simulation (a
huge cross product of events); 1 of them could have been hit by enhancing
the SW simulation environment.
Jasper's support team was great and very responsive to questions we had.
For example:
- gated reset in 2 different clock domains
- minor RTL parse issue
In the end, we renewed our Jasper licenses as it seemed like the best fit
for our needs. We are planning on expanding its use on the next project
and are working with Jasper to train more users for that purpose.
- Homayoon Akhiani
Azul Systems, Inc. Mountain View, CA
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