( ESNUG 451 Item 10 ) ------------------------------------------- [02/08/06]
Subject: ( ESNUG 433 #5 ) One User's Follow-Up Benchmark of DC 2005.09 XG
> The results comparing 2003.06 with the Nighthawk 2004.06 beta. The test
> design is a large, critical block in one of our 130 nm chips. We got 3X
> faster runtime with more then 5X reduction in TNS with the biggest
> improvement in capacity.
>
> DC 2003.06 DC 2004.06 beta Nighthawk
> ------------ -------------------------
> Runtime 61 hrs 20 hrs
> Area (cells) 1.1 M 1.1 M
> WNS -0.5 ns -0.15 ns
> TNS 1318 ns -229 ns
>
> Of course nothing is for free. We did have to make one change to our
> scripts; removed any explicit use of uniquify commands. DC now does this
> automatically. Actually, this single change made our scripts much easier
> to maintain, and the runtime improved drastically.
>
> - Sam Bishai
> Cisco Systems Kanata, ON, Canada
From: Sam Bishai <sbishai=user domain=cisco spot calm>
Hi John,
Thought I'd follow up with yet another DC benchmark. I beta-ed DC 2005.09
and was impressed with the results I got. I tested 10 blocks implemented
in 3 technologies from 2 vendors, 2 in 130 nm and 1 in 90 nm. Comparing
these results with DC 2004.12, I observed:
1. The area is smaller in all test cases. The average improvement seen
was 3.5% with one block improving by 7.6%. Since all the blocks are
memory intensive these results are particular impressive.
2. In all cases, I saw an improvement in WNS, TNS, and a significant
reduction in the number of violating paths.
3. One design had a WNS of 0.04, TNS of 0.8 and 62 violating paths in
DC 2004.12 had passed cleanly in DC 2005.09.
In all the test cases the new XG-mode was turned on. An improved runtime
was consistently seen as compared to the old version. In all designs with
one exception the memory usage was also smaller. The XG-mode results in
DC 2005.09 are much better than the ones I had seen when testing this mode
in the previous version.
We are currently in the architectural phase of a new chip and I was tasked
to test and verify changes required to take and old design and run it at
twice the speed at 90 nm. The added features in design_vision were a
tremendous help. The Timing Analysis Driver helped identify paths that
would require pipelining and where the flops would be inserted. The ability
to inspect the paths similar to PrimeTime was of great help in the RTL
implementation stage. This 2005.09 release of DC looks promising.
- Sam Bishai
Cisco Systems Kanata, ON, Canada
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