( ESNUG 451 Item 7 ) -------------------------------------------- [02/08/06]
Subject: ( DVcon 05 #15 ) Three Engineers review the Eve ZeBu Accelerator
> Skim off those 76% no's and you get the 2005 emulator/accelerator use.
>
> 2005 - Cadence Palladium : ############################## 59%
> Verisity Axis : ########## 20%
> Mentor IKOS/Celaro/Vsta : ################ 31%
> EVE ZeBu : ####### 15%
> ProDesign : ### 6%
> Aptix : ## 4%
> Tharas Hammer : 0%
> Pittsburgh Sim : 0%
> Aldec Riviera-IPT : 0%
>
> Holy moley! Cadence Palladium jumped waaaaaay up from 39% to 59%! Whoa!
>
> - from http://www.deepchip.com/items/dvcon05-15.html
From: Rakesh Mehta <rakesh_mehta=user domain=ltx spot calm>
Hi, John,
We have used Eve's ZeBu-XL card for close to 2 years now; we use it strictly
for simulation acceleration. Our design is approximately 500K gates, but we
need to map multiple instances of our ASIC, generally 2 or more depending
upon the number of FPGA's. Our design is also memory intensive, both
internal to the chip and external. As far as benchmarks for the different
ZeBu options, we found:
1) HDL/SystemC co-emulation gave us around 3-4x performance compared
to pure RTL simulation
2) Transactor co-emulation gave us max performance, and we got about
500X improvement over pure RTL simulation. This is the mode we use,
since it is the fastest option.
It took me a little over 2 months to have a running ZeBu verification
environment, which was a surprise. But since we always reuse our IP and
build on it, the environment didn't change for future projects. One area we
found that needs improvement is that once you start using external memory
that's on the ZeBu board, the performance goes down (this may be improved in
the newer boards).
The best things about ZeBu XL are:
1) Excellent software, we haven't had a need to patch its installed
software...no bugs have been found in it yet.
2) Nice debug options. For example, ZeBu's dynamic probing HW debugging
feature is very useful to debug problems, as we can easily add/remove
signals without having to re-compile.
3) Good design partitioning tool.
I had a constrained random testbench that ran on ZeBu for weeks, and it
caught cases which were not tested by our Verilog test-environment, enabling
us to fix the bugs prior to sign-off. I have had a great overall experience
using ZeBu and would recommended it.
- Rakesh Mehta
LTX Corp. San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Little ]
Please keep me anonymous.
Before moving to Eve, we set up a comprehensive benchmark of Eve ZeBu-XL,
ProDesign Platinum, and Aptix MP4CP because of our absolute requirement for
MHz+ speed prototyping, which fundamentally excluded Cadence Palladium and
Mentor VStation.
ZeBu won the evaluation hands down, based on final speed, time to bring
up, ease of use, debug capability, and quality/reliability of the product's
hardware and software. It did well in all these categories, with speed
being our paramount category.
We now use ZeBu in 3 different modes:
1) transactors
2) co-simulation and
3) pure In Circuit Emulation with target board.
It works well in all 3 modes.
ZeBu's has a dynamic probing debug let you look at sequential elements of
the design without having to recompile the design. Its triggering and
tracing is pretty good.
I would like Eve to get a handle on the complete RTL to in the box. And
then to debug it, so it wouldn't be a bottleneck for us any longer.
As for my overall assessment, ZeBu has saved us countless re-spins. Our
work with ZeBu-ZV and -XL is an integral part of both our SW and HW
development. It is vital because we must do both of them in parallel, not
serially. Other companies may be able to wait for the software until after
the silicon is back, but we simply can't.
Eve recently released ZeBu-UF and claims it will double their speed. In
my experience with ZeBu-ZV, we ran 1.5 million gates in 12.5 MHz; so with
ZeBu-UF we should able to run 3 million gates in 25 MHz. We have now used
2 generations of Eve's ZeBu products (first -ZV, then -XL), and everything
went so smoothly that we have decided to upgrade to this -UF version.
- [ Chicken Little ]
---- ---- ---- ---- ---- ---- ----
From: [ The Horse With No Name ]
Hi, John,
We use Eve's ZeBu-XL. The ASIC design that we needed to verify had a huge
number of images to test, so we really needed a hardware accelerator. We
evaluated ZeBu in August 2004, and bought it that November. Our main reason
for selecting ZeBu as our hardware accelerator was because we could get
reasonable acceleration with it without developing transactors.
With all of the other accelerator boxes, transactors (data channels) between
the PC and the box were required to get top performance. Eve told us that
full speed would also require transactors, but we could get some performance
improvement without them.
It took us 2 weeks to set up ZeBu-XL for the first design. We later
developed the transactors, which took about a month, to achieve maximum
speed benefits. Once this was done, new design iterations took about 2-4
hours.
We used ZeBu's transaction-based co-emulation mode. Our project was for a
compression design with a lot of signal processing; it had about 4 million
gates. We ran ZeBu at about 3.5-4 MHz. We ran 131,500 images through
ZeBu -- each one would take 45 minutes in a simulator vs 1 sec with ZeBu.
So basically, what took us 24 hours with ZeBu would have taken us 11 years
on a fast Solaris box! In general, ZeBu's performance improves with less
partitioning; our design used only 2 FPGAs versus 6 FPGAs available in
the box.
In the beginning -- before using transactors -- we used ZeBu's dynamic
probes and static probes. First we debugged the design functionally using
end-to-end simulation; then we imported the working design into the box.
ZeBu's probes were useful to basically debug our design to work in their
box as it wasn't working the first time. ZeBu can be used for functional
debug also, but we did it this way to better separate problems with the
design itself from problems with bringing it up in box. Now that we use
transactors however, we find that viewing probes slows down the simulation
a lot.
Our methodology was to run the 131K images through ZeBu XL, and if it flags
any problems, we then debug those problem images with the simulator.
ZeBu's turnaround time could still be improved. I would like to see a new
design only take a couple of hours, and with ZeBu it is closer to 4 hours.
We have ways to improve our speed, but it would be nice for the tool to do
so. Other boxes have faster turnaround time, but don't have ZeBu's speed.
Eve's boxes aren't that expensive, and actually ZeBu was one of the cheapest
ones I evaluated. However, it could always be cheaper; reducing the price
further might help more people move from using boards with FPGAs to ZeBu.
ZeBu's biggest strength is its speed. We have seen 3.5-4 MHz.
We now have 3-4 different groups in our company who have used ZeBu; they
picked it up on their own just by reading the literature and without the Eve
application engineers being involved. This is credit to Eve... so far the
software isn't buggy, the literature is useful and there are not a lot of
steps involved nor too many intermediate files needed.
Anon please.
- [ The Horse With No Name ]
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