( ESNUG 451 Item 4 ) -------------------------------------------- [02/08/06]
Subject: ( ESNUG 450 #3 ) DC 2005.09 did NOT change; it might have a bug
> DC would merrily go along and fix the timing on as many paths as it could
> that were within your "critical range" setting regardless of the domain
> on which they existed.
>
> Using the latest version (2005.09) it seems that if you have a domain in
> your design that has a path that can't meet timing, ALL other domains and
> paths are now NOT worked on. You can end up with scads of failing paths,
> in a design that when using the previous version of DC, compiled quite
> happily...
>
> - Gzim Derti
> Agere Systems Allentown, PA
From: Yanbing Li <yanbing.li=user domain=synopsys spot calm>
Hello John,
I wanted to assure your ESNUG readers that there has been no change to the
"set_critical_range" command or its functionality in DC 2005.09.
- DC treats each clock domain as a separate path group and optimizes
them independently.
- There is no change in the handling of the critical range.
- Within a clock domain, I/O and reg2reg are treated as a combined
path group unless the user explicitly defines them as separate path
groups.
As to the problems reported by Gzim Derti in his "User resents Secret
Ambush Changes in how DC Fundamentally Works" post, we are working with
him to identify the issue that is resulting in the behavior that he is
seeing and find a solution.
Of course, there were a ton of other changes in DC 2005.09 that result in
5% smaller area & better timing plus 20% higher capacity & faster runtime.
DC 2005.09 incorporates a new intelligent logic structuring algorithm
that provides accurate timing view across hierarchical boundaries and
macros. This new algorithm also allows the tool to revert to abstract
Boolean logic when aggressive timing strategies are needed and results
in improved QOR.
With enhanced Case Statement optimizations, you no longer need to use
the infer_mux pragma. Design Compiler can now automatically infer MUX_OPs
resulting in improved area QoR with equal or better delay.
In the datapath optimization area, we extended datapath extraction to
variable shift operators (<<, >>, <<<, >>> for Verilog and sll, srl,
sla, sra, rol, ror for VHDL) and allows them to be optimized as part of
the datapath when you use the compile_ultra command. This enhancement
provides you with higher flexibility and improved QoR with datapath.
The optimize_registers command has a new option, -latch, that allows you
to retime level-sensitive latches.
- Yanbing Li
Synopsys DC CAE Manager Mountain View, CA
Index
Next->Item
|
|
