( ESNUG 451 Item 1 ) -------------------------------------------- [02/08/06]
From: Stu Sutherland <stuart=user domain=sutherland-hdl spot calm>
Subject: Cliff & Stu -- Help us merge Verilog & System Verilog standards
Hi, John,
We have a question for your readers that needs an answer no later than
February 15th.
The IEEE 1800 standards committee is debating the value of merging the IEEE
1364-2005 Verilog standard and the IEEE 1800-2005 System Verilog standard.
System Verilog is not a stand-alone language; System Verilog is a large set
of powerful extensions to Verilog. One can use the Verilog reference manual
as a stand-alone document. But, to use the System Verilog reference manual,
one must have both the Verilog and System Verilog manuals open at the same
time.
On the standards groups, when we first began specifying these extensions, it
was with the intent that there would be one IEEE "Language Reference Manual"
(LRM), that contained all of Verilog plus all the extensions. The powers
that be in the IEEE Standards Association that oversees EDA standards,
however, decided that it would aid EDA companies in implementing the System
Verilog extensions if those extensions were first documented separately from
the base Verilog language. The stated plan was that once the extensions
were officially ratified, the Verilog and System Verilog LRMs would be
merged into a single Language Reference Manual.
The System Verilog extensions have been approved as an official IEEE
standard. The IEEE 1800 standards Working Group, which has responsibility
for both the 1364 Verilog and 1800 System Verilog LRMs, is now debating
whether or not it is worth the time and effort to actually merge the two
documents. Many of the 1800 Working Group members (mostly EDA companies)
feel that only EDA companies actually use the IEEE reference manuals. They
think most users (that's me and you) of EDA tools only look at product
documentation, training guides, books, and not the IEEE LRMs. Therefore,
a number of 1800 Working Group members (a slight majority) feel that taking
the time to merge the two LRMs has no value to EDA tool users, and should
not be done.
Cliff Cummings and I disagree with this opinion. We think that design and
verification engineers do use the IEEE standard Language Reference Manuals.
We also think that having the Verilog base language and all the official
extensions to Verilog documented in a *single* Language Reference Manual
will benefit design and verification engineers. I want to hear from ESNUG
readers as to whether or not I am right, or am completely off base.
Please send me at e-mail (stuart@sutherland-hdl.com) answering the three
following questions:
1) My primary work is _____________________________. E.g.: design
engineer, verification engineer, product engineering manager,
EDA tool development engineer, EDA engineering manager, ...
2) How often do you refer to the official IEEE Language Reference Manual
for an EDA standard, such as Verilog, System Verilog or VHDL? Please
answer "never", "occasionally", or "frequently".
3) Would merging the Verilog and System Verilog Language Reference Manuals
make it easier for you to work with these standards? Please answer
"yes" or "no".
Additional comments on this topic in general, are welcome.
Please include the words "Merging Verilog and System Verilog LRMs" in the
subject line, so that I can easily find and sort your message.
NOTE: I need your answers and opinions no later than 15 February 2006. The
1800 Working Group is meeting shortly after that date to make a final
decision on whether or not to merge the two LRMs. If you care about what
the standards committees are doing, then this is your opportunity to give
the IEEE 1800 Working Group some direction. I pay the IEEE Standards
Association's high annual dues so that I have a vote on the Verilog and
System Verilog standards, and will make sure that your feedback is heard.
I will send a summary of what I learn from you, and the final 1800 working
group decision, to John to publish in ESNUG.
- Stu Sutherland
Sutherland HDL Portland, OR
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