( ESNUG 448 Item 8 ) -------------------------------------------- [11/11/05]
Subject: ( ESNUG 446 #17 ) Synopsys CCS Only Duplicates Cadence/Magma ECSM
> In order to have a more accurate model for voltage variations, Cadence
> and Magma promote ECSM extension for Liberty format while Synopsys
> promotes CCS. I am looking for other users impressions and evaluation
> results of these models, considering accuracy and speed of timing
> analysis and ease and speed of library characterization.
>
> - Ori Chalak
> Analog Devices Israel
From: Li-Siang Lee <llee=user domain=cortina-systems spot gone>
Hi, John,
We did a comparison of ECSM vs. .db and HSPICE simulation a year ago using
TSMC 0.13G process with Artisan STD library.
We generated timing reports (10 reg-to-reg paths) using PrimeTime+DB+SPEF,
PrimeTime+SDF (using Cadence SignalStorm & ECSM+SPEF) and HSPICE simulation
with SPEF. Both PrimeTime+DB and PrimeTime+SDF results are with 2% of HSPICE
simulation. From this test, we concluded that ECSM is as accurate as .db.
We also did a multi-voltage (0.8v supply driving a 1.2v supply gate) PT+SDF
(with 3 voltage ECSM model provided by Artisan) run, the result correlated
very well with HSPICE simulation. At that time, I don't think you could
perform such STA run using PrimeTime+DB+SPEF.
There is no runtime advantage using PrimeTime+SignalStorm+ECSM+SPEF since you
still want to load in SPEF in PT if want to get to get the correct wire
loading on your PT report.
No comment on lib characterization since we did not run it (provided to
us by Artisan.)
- Li-Siang Lee
Cortina Systems, Inc. Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: Kenny Tung <ktung=user domain=amcc spot gone>
Hi, John,
Our COT tool flow requires us to use both CCSM and ECSM. ECSM is used to
build the Magma Volcano database for Blast Fusion and CCSM is used to build
the Synopsys timing model for PrimeTime-SI.
I cannot comment on the difference in accuracy between the two formats,
because we haven't done that analysis yet. It takes a lot of work to do
those correlations. However, from a file size standpoint, we have found
ECSM to be one half the size of CCS.
- Kenny Tung
AMCC San Diego, CA
---- ---- ---- ---- ---- ---- ----
From: [ Comic Book Store Guy ]
Hi, John,
I must be anon.
We have been using ECSM modeling for tapeouts. Our main reason for using
ECSM was that we had parallel drivers, and non-linear delay modeling (NLDM)
was not accurate enough; modeling waveforms using a current source method is
much more accurate. We have noticed that our accuracy is within 2-3% of
SPICE for ECSM versus more than 7% for NDLM.
IR drop and other affects can be better modeled with ECSM versus .lib. But
one limitation I found with it is that we can't use it for memory or complex
cell characterization.
In the end ECSM has worked pretty well for us for 130 nm and we will continue
to use it for 90 nm. If adequate resources for both licenses and machines
are available, it only takes us 3-5 days to build a 500 cell library, which
is reasonable.
- [ Comic Book Store Guy ]
---- ---- ---- ---- ---- ---- ----
From: Robert Jones <rjones=user domain=magma-da spot gone>
Hi, John,
In response to Ori's question on ECSM/CCS formats, current source modeling
handles 2 areas in particular better than NLDM:
1) on long routes where we see the slow RC tail-offs of highly resistive
interconnect
and
2) for high-performance, low-power designs which require support for
multiple voltage domains without the heavy characterization bottleneck
that killed the equation-based SPDM.
As Ori indicates, there are currently two competing current source model
formats, ECSM and CCS.
ECSM in its current form was developed by Cadence and Magma. It has been in
commercial use for over 4 years and has been an extension to the .lib
standard for over 2 years. Over 100 working chip designs have taped out
using ECSM. Major library and silicon suppliers such as Artisan (ARM) and
TSMC offer ECSM models, and both Magma and Cadence offer off-the-shelf ECSM
characterization and commercial chip design software. ECSM is a modeling
method that supersedes only the table model within the .lib file, and is
represented as a property field within a .lib file. (So existing software
tools which do not support ECSM but do comply with the .lib standard are
ECSM-compatible -- though not as accurate.)
Finally, ECSM is now an open standard outside of the strict control Cadence
or Magma.
In contrast, Synopsys only introduced the CCS format in the past year, with
tool support very recent, and the number of tape-outs relatively unknown.
Any differences CCS offered could likely have been added as enhancements to
ECSM without jeopardizing the existing industry investment in development
work (flows, libraries, tools).
This brand new .lib extension (CCS) came at time when a successful and open
extension (ECSM) already existed. If we don't address how an industry
standard format like .lib is updated, we will continue to live with multiple
library formats that force us to characterize, translate, and move around
duplicate data to get designs out the door. Unfortunately, supporting both
formats requires additional verification work that is an ongoing cost.
These added costs have the potential to far exceed development costs.
I don't see any "win" here for the fabs, EDA vendors, nor end-users for a
second current source model format.
- Robert Jones
Magma Design Automation Austin, TX
---- ---- ---- ---- ---- ---- ----
From: [ The Quiznos Talking Baby ]
Hi, John,
Please keep me anonymous.
We are evaluating ECSM as a potential aid in timing analysis for designs
that operate at continuously variable voltage and also to see if it can
improve accuracy in parasitic-dominated path delay and in cases with
parallel shorted drivers.
Right now I can only comment on the library characterization issues, since
we won't complete correlation work until next quarter. The ECSM library
characterization is a very simple extension since the simulations performed
for delay/slew characterization are exactly the same as what is needed for
ECSM anyway.
For us it is about 1 day of work to add the ECSM format to our library
characterization for combinatorial cells and flops. I should state that we
have our own library characterization Perl code rather than using a
commercial characterization tool. There is little impact on the
characterization time since the ECSM portion just amounts to a few
additional measure statements per HSPICE simulation.
I am not as familiar with CCS. On the surface, the CCS model looks more
complicated. Certainly for us to support the arc-based receiver capacitance
model would require a change in the way we currently characterize pin
capacitance. The CCS driver model characterization is probably not much
more difficult to implement than ECSM.
We will ultimately have to try out both ECSM and CCS since our signoff
timing tool is PrimeTime which doesn't support ECSM. (We use Cadence P&R
tools, so we also have their timing engine which supports ECSM.) We don't
yet have data on the relative accuracy and performance of standard Liberty
table lookup vs ECSM or CCS.
- [ The Quiznos Talking Baby ]
---- ---- ---- ---- ---- ---- ----
From: Edmond Macaluso <edmond=user domain=z-circuit spot gone>
Hi John,
From our experience with Cadence/Magma ECSM models, I would say that the
benefit is quite significant, and it is a major advancement in timing
accuracy; however, if not used properly, users could easily end up with
failed chips. The risk is higher with ECMS and Synopsys CCS simply because
they are more complicated and because, in some cases, you are using more
advanced design practices, such as voltage islands.
Since these are relatively new model technologies, a little history may
help in understanding the status. Cadence added ECSM format extensions in
Liberty over 2 years ago. Since then, we have seen an increase in interest
within our customer base, especially related to 90 nanometer and below.
This year, Synopsys announced CCS format extensions for Liberty. ECSM and
CCS formats are similar enough that some members of the Si2 Open Model
Coalition, who spoke at a forum at DAC, recommended merging the 2 formats.
We've created models for several applications in ECSM format. ECSM
basically enhances the way input pin capacitance and output signal
transitions are modeled. The advantage is quite significant for two
very important timing situations:
1. improved accuracy for timing of long nets
2. improved accuracy for variations in supply voltage
Improved timing accuracy for circuits driving long nets should be verified
for your technology by comparing gate-level timing to SPICE simulations. You
may or may not see a significant difference, depending on the technology.
You definitely will want to verify the difference since margin was set based
on using standard models and needs to be re-evaluated when making such a
fundamental change to models.
Additionally, current-source models enable a new set of design methods for
reducing power consumption at smaller feature sizes. For example, assuming
you have verified the current-source model accuracy, then the following
design methods may now be employed:
1. Operating at non-typical supply voltages (over-drive or under-drive)
can significantly change the power requirement for blocks.
How to do it: ECSM, or a more time consuming complete library
re-characterization with multiple corners of standard NLDM timing
models, would be required to get accurate timing.
2. Operating with multiple supply voltages (voltage islands) on the same
chip allows different sections of a design to operate with a different
speed/power trade-off.
How to do it: ECSM models would be most efficient in this case,
compared to multiple library corners.
3. Operating clock networks more aggressively. Accurately accounting for
supply voltage on clock network circuits is critical for calculating
correct clock skew on the clock network. More accurate clock timing
information reduces the required margin and results in faster and
easier timing sign-off.
How to do it: Using ECSM, or running SPICE on the clock network, are
the only practical solutions for calculating correct clock skew in the
context of a voltage gradient.
To avoid a chip failure, you need be careful with these methods. Models
must be accurately characterized and verified, which is particularly
difficult at different voltages. In addition, the tool flow becomes more
complex for optimization and timing sign-off
I would be particularly careful about how timing constraints, such as setup
and hold times, are modeled at different design voltages, since ECSM models
do not address timing constraints at different voltages. If the
constraints for your circuits change significantly with voltage, then that
could be a problem and you may need full characterizations at appropriate
multiple corners.
Note that these new models do not directly affect SI analysis. SI analysis
and repairs are performed orthogonally during timing sign-off; however, the
timing analysis during SI should support the appropriate ECSM or CCS models.
We also could envision some designers wanting to use both ECSM and CCS
models in their design flow if they have a mixed Cadence/Synopsys flow.
If you do the up-front work comparing ECSM timing, CCS timing, and SPICE
path timing, for your technology, then this approach should end up with
well-correlated results. However, remember that different timing tools are
being used in this case, and that these tools employ proprietary methods
that could produce significantly different results from models that
appear similar. Also, it's a good idea to keep these tests around so you
can compare new releases of the timing tools.
- Edmond Macaluso
Z Circuit Automation Newark, CA
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