( ESNUG 448 Item 3 ) -------------------------------------------- [11/11/05]
Subject: ( DVcon 05 #11 ) FPGA Design and Those GUI Design Entry Tools
> 2005 - "How about graphical design entry tools like Summit
> Visual Elite or Mentor HDL Designer (Renoir)?"
>
> don't use : #################################### 89%
>
> Summit Visual Elite : #### 4%
> Mentor HDL Designer : #### 4%
> homebrew GUI tool : # 1%
>
> - from http://www.deepchip.com/items/dvcon05-11.html
From: Richard Hein <richard_hein=user domain=agilent spot gone>
Hi John,
While I agree that graphical entry tools are not widely accepted, I
wouldn't go so far as to group them with pet rocks. Seems like I'm in
the minority of people who do actually find them an effective design
entry method so I felt compelled to speak up. Seems like graphical entry
is an either love it or hate it thing.
I've been designing FPGAs for 13 years, so long in fact I remember doing
designs graphically all the way down to the gate level entirely with
Mentor Design Architect. I admit my age is a factor in why I like
graphical entry as I remember some of the benefits that were lost when
we moved to HDL. I recall when we adopted HDL there was also reluctance
to move to HDL but eventually everyone caught on to the idea.
After we made the move to HDL, using graphical entry sounded like a step
backwards. After all we were told HDL is the way to go now so why would
we want to go back to schematics. While I didn't miss entering gates
graphically, I did miss the visualization of schematics and then having
to type every signal name multiple times (VHDL). I find graphical entry
combines the best of both worlds.
I only use it for structural design entry. Since we use VHDL I can draw
a block diagram and add a few signals and generate 100s of lines of
structural code quicker (and with no typo or cut and paste type errors
since it's graphical) than typing all the structural code and
declarations manually plus the design is automatically documented with
an up to date detailed block diagram. My colleagues have appreciated a
single sheet block diagram instead of 100s of lines of text.
Working with HDL structural code is like working with a PCA board
schematic without nets, with component pins only connected with net
names. If HDL structural code works well then why aren't PCA board
designs entered in text also? Think of the money you'd save on EDA
tools.
I also use the graphical tools to import a design to better understand
the design. Granted a computer generated schematic is ugly but I've
found the process of cleaning it up a great way to absorb how the design
is structured so time wise it ends up faster in the long run.
Also the newer releases of HDL designer integrate with non-HDL designer
designs reasonably well. We have a custom design environment with many
people working on the one FPGA and I found it possible to use HDL
designer in conjunction with non-HDL designer entered designs.
Having said all that, despite my enthusiasm for graphical entry I have
never been able to convince anyone else to take it up. I agree the
barrier is that it's another unknown tool to learn and a perceived step
backwards. You've just got to take the leap and give it a go on a design
to see if it works for you.
- Richard Hein
Agilent Canada Vancouver, Canada
---- ---- ---- ---- ---- ---- ----
From: Blake Scott <blake_scott=user domain=nsroc.net>
Hi John,
I have been designing some Altera circuits (CPLDs) and I use lots of state
machines. The way I learned it in school years ago was to draw the machines
using state diagrams. The Altera Quartus II program doesn't allow that, so
I was thinking of using a 3rd party program like Mentor Graphics Author or
Aldec Active-HDL. Am I heading the right direction, or am I just making my
life more complicated? I am otherwise satisfied with the Quartus.
- Scott Blake
NASA Sounding Rocket Eng. Wallops Island, VA
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