( ESNUG 447 Item 16 ) ------------------------------------------- [09/26/05]
From: Stuart Sutherland <stuart=user domain=sutherland-hdl spot calm>
Subject: Stu's System Verilog Assertions Class in Boston has Openings
Hi, John,
I thought you might want to know that there are still a limited number of
seats available in the upcoming 2-day training workshop in Boston, MA,
"System Verilog Assertions for Design and Verification Engineers".
This is my 2-day workshop provides highly focused training on the System
Verilog temporal assertions language, with an emphasis on how and when to
effectively use assertions.
The workshop will be held in Chelmsford, Massachusetts, September 29-30.
Attendees receive a comprehensive System Verilog Assertions training guide,
plus the book "Handbook to System Verilog Assertions".
- Stuart Sutherland
Sutherland HDL Inc. Tualatin, OR
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