( ESNUG 447 Item 7 ) -------------------------------------------- [09/26/05]
Subject: ( SNUG 04 #18 ) Three Users Benchmark Power Compiler plus XG Mode
> We've used Power Compiler when it was rolled under the hood of DC.
> Overall I was quite happy with Power Compiler. I'm not sure about how
> well it compares with silicon though. The only painfull part is
> re-compiling simulator executables to record switching activity.
>
> - Gord Allan of Carleton University (Canada)
> http://www.deepchip.com/items/snug04-18.html
From: Jeff Shabel <jshabel=user domain=qualcomm spot calm>
Hi John,
We have used Power Compiler for several years on many designs. With power
management being one of our top design criteria, our use of Power Compiler
has picked up over the years. Since clocks can consume 40-50% of total
dynamic power, we needed to drastically reduce clock tree power early in
the flow.
We've found via static analysis on our recent chips that max clock tree
power savings due to Power Compiler clock gating can range from 25-75%.
(Maximum clock tree power savings occurs when all of the clock gating cells
are in a gating state. Obviously, real clock tree power savings will be
less than the maximum when our blocks are operating normally.)
As a benchmark, we ran two identical blocks on two different chips, one
that used Power Compiler and one that did not. The only main difference
between the blocks on these two chips was the use of Power Compiler.
Running these blocks in a real functional mode on silicon showed that
overall dynamic clock tree power was reduced by 31-40% on the chip that
used Power Compiler.
Overall, we are pleased with the results of Power Compiler. If anyone is
interested, I will be presenting a paper on it at Boston SNUG next week.
It will present a more detailed analysis of clock trees and power
consumption associated with them. I will also present a method to analyze
clock tree power using PrimeTime and show correlation to silicon.
- Jeff Shabel
Qualcomm, Inc. San Diego, CA
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Little ]
Hi John, could you please keep me anonymous?
We have been using Power Compiler for 2 years now. For our first design we
were mostly concerned about reducing dynamic power at the RTL level with
clock gating and then measuring the average and peak power accurately at
the gate-level using PrimePower.
We were able to get reasonable (45%) power savings using Power Compiler
and are satisfied with its results.
In the future, we'll be looking at leakage power with Power Compiler as we
move to smaller geometries.
- [ Chicken Little ]
---- ---- ---- ---- ---- ---- ----
From: Vikram Somaiy <somaiya464=user domain=oki spot calm>
Hi, John,
We use Power Compiler in out flow for RTL Power analysis, clock gating
and generating reports necessary for our IR Drop flow. Our experience
with Power Compiler XG mode:
- No changes in commands for XG mode. Hence migration from TCL to
Power Compiler XG is easy.
- The power for post layout netlist reported by Power Compiler falls
within 200 mWatts of backend static power using a variety of tools.
- The XG mode power analysis is very fast. On a 800,000 instances
(3.2 million cell unit area) design, DC TCL mode used to take
about 8 hours of runtime on Linux machines to generate all the
reports we need for IR Drop analysis. The DC XG mode reduces that
time to mere 45 minutes. (That decrease in run time lets us now
have multiple runs across min and max corners.)
Also, the XG mode can now write out an SAIF file with propagated switching
activity on pins/nets/instances that were missing switching activity
annotations in the original SAIF file. This resolves the problem if any
third party tool is not able to propagate switching activity.
- Vikram Somaiy
Oki Semiconductor San Jose, CA
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