( ESNUG 447 Item 4 ) -------------------------------------------- [09/26/05]
From: Jay Pragasam <jay.pragasam=user domain=open-silicon spot calm>
Subject: Why Did Synopsys Bail Out on its RTL-To-Placed-Gates Methodology?
Hi John,
When physical synthesis emerged, Synopsys came out with both RTL2PG and
Gates2PG flows claiming each resulted in different quality of results
based on the design and did not vehemently advocate one over the other.
But all the other vendors (Cadence, Magma, etc.) who also called their
tools "physical synthesis" started from the netlist gates and relied on
some logic synthesizer to give good quality of results.
Though it did seem that RTL2PG was the right thing to do as technologies
evolved, I see that even Synopsys has moved out of that doctrine by making
IC Compiler a strictly Gates2PG tool, much like Blast Fusion or PKS.
Does this mean RTL2PG is dead and Synopsys faltered in its effort to
squeeze the real juice out of RTL2PG? Or were the other players smart to
visualize that Gates2PG is clearly the way to implement better chips?
- Jay Pragasam
Open-Silicon, Inc. Sunnyvale, CA
Index
Next->Item
|
|
