( ESNUG 446 Item 1 ) -------------------------------------------- [09/01/05]
From: Tom Weiss <tweiss=user domain=ati pot calm>
Subject: Cadence Palladium II Benchmarks Honking Fast with Mondo Capacity
Hi, John,
Our ASIC verification and firmware development group shifted to Palladium
over a year ago. We recently upgraded to a Palladium II. (Cadence Sales
said the Palladium II was supposed to be up to twice as fast as their
Palladium I.) We also moved from an 8 M gate machine to a 16 M gate
machine to allow us to run test two ASICs simultaneously.
The Palladium II exceeded our expectations. Our video decoding block level
testbench had grown too large for the FPGA board we had been using and
simulations were taking over a week to complete. We initially ported the
testbench to our Palladium I using the simulation acceleration mode. The
time to run our critical test streams went from over 7 days to 20 minutes.
Over succeeding days, we shifted to the synthesizable testbench emulation
mode, and the moved the effort to Palladium II. The test time dropped from
20 minutes to 3 minutes with an effective clock speed of 1 MHz.
We've now been able to add significantly longer vectors and test additional
modes to fully test the block and still keep run times well under an hour.
Another key feature is the ease of script development. The designer
modified his simulation testbench so that he can use a command line option
to run tests either in simulation or emulation. The script loads the design
and test vectors, set ups the test registers, continually refilling the
memory with new data as the test executes, and reading data out of memory
and storing it to a file. With the logic design group able to support their
own emulation work, we've reduce the amount of resource time focused on
emulation.
The biggest surprise was size of designs we could load into Palladium II.
Though we moved to a box twice as large as the Palladium I, compression
has been greatly improved. In Palladium I, our simultaneous use was limited
to our larger ASIC and a block level testbench. With Palladium II, I can
run 4 simultaneous instances of our 5-6 M gate ASIC. This has allowed us to
jointly share the box with ASIC, firmware and software engineers across
3 different development sites at the same time.
With assertion support becoming available in upcoming releases, we will
continue to start moving the Palladium II earlier and earlier in the
development cycle. Now our problem is coordinating the sharing of this box
across projects and development phases effectively. :)
- Tom Weiss
ATI Yardley, PA
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