( ESNUG 443 Item 1 ) -------------------------------------------- [04/15/05]
Subject: ( ESNUG 441 #8 ) VStation Benchmarks 3x Faster Than Palladium
> I believe FPGA-based architectures have run out of steam to handle
> multi-million gate designs effectively. Palladium's differentiating
> element is that it is a processor-based technology. All in all
> weighing both positives and negetives, we are very happy with
> Palladium and I would recommend it to other users.
>
> - Narendra Konda
> nVidia San Jose, CA
From: Fiona Chua <fiona.chua=user domain=philips spot gone>
Hi, John,
We already had Mentor Graphics/IKOS VStation V15m boxes set up on site when
the boys from Cadence/Quickturn started dangling a Palladium PD-4 in front
of us. To cut a long story short, we took the bait and did a comparison
between the two. Here is the summary of what we found. Bear in mind that
the report is dated December 2003, and technology has since moved on. There
are now Palladium PD-16G and Vstation Pro boxes, which have much bigger
capacities. Anyway, for In-Circuit Emulation (ICE):
Cadence Mentor
Palladium (PD-4) VStation (15M, 9 boards)
---------------- ------------------------
Platform Processor based Xilinx FPGA based
Max Capacity 16 M gates 15 M gates
Max Memory Capacity 8 G bytes 144 M bytes
Max I/O pins 2816 4608
Speed 200-600 kHz 500 kHz -2 MHz
Dimensions (HxWxD cm) 100x135.9x105 69.85x54.61x91.44
Power Requirements 220 VAC, 30A, 50/60Hz 186-264 VAC, 16A, 47-63Hz
The PD-4 has a slightly higher capacity and a much larger internal memory
capacity. The V15m on the other hand has a higher IO capacity and is faster,
physically smaller and consumes less power. For the evaluation, the same
database was downloaded into both emulators and set up to run in ICE mode.
This database consists of a Digital Video Processing ASIC and its two
companion chips, forming a complete digital TV system solution. Its link to
the outside world includes interfaces to a DDR target board and a PCI link
to a PC. Evaluation results of PD-4 vs. V15m:
Cadence Mentor
Palladium (PD-4) VStation (15M, 9 boards)
---------------- ------------------------
Compile Time ~1 hour ~3 hours (compile+P&R)
Run Time 1 min 54 sec 40 sec
Capacity Utilization 8.96 M gates 12.96 M gates
RTL support Yes Yes
Support of Asynch Clk No Yes
Ease of Design Debug good could be better
HW/SW Reliability okay improving
On-Site Support very good very good
Extra HW: Sun workstation Sun workstation
+ PC farm (for P&R)
Physical Requirements BIG, good much smaller,
source of heat less power consumption
in winter
Being processor-based, the Palladium worked very much like a super-fast
simulator. Its compilation time is quick and its user interface boasts of
a very friendly Debussy schematic viewer with the ability to probe signals
on the fly without having to de couple the emulator from the ICE mode.
For a database with a constant ASIC gate count, the Palladium requires a
lower capacity utilization than the VStation, which requires extra logic
to implement its 100% signal visibility mode.
The VStation, on the other hand, is FPGA-based and requires a P&R step,
which prolongs its compilation time. Because it is FPGA-based, the
VStation is very particular about the type of clocking structure it can
accept. It uses its own in-house debug tool suite, which unfortunately is
not as friendly as the Debussy solution. But to be specific, as certain
Mentor AEs like to point out, VStation does offer the use of Debussy, but
only with VHDL RTL codes. Mentor does intend to replace its debug
environment with a full Debussy solution but that is still to come.
The VStation also requires the disabling of its IOs when viewing signals
that were not explicitly probed. This proved to be most inconvenient as
our processor-based software takes a while to set up; something which must
be repeated every time the emulator is taken out of its in-circuit mode.
However, the VStation is fast. We measured the time taken for the software
to be downloaded into DDR memory, fetched and processed by the internal
processor. The result showed that the VStation was nearly 3 times faster
than the Palladium. The way the two emulators handle clocking is vastly
different and worth a mention here. The VStation allows for the use of
14 external asynchronous clocks, which can be routed directly to each FPGA
within the emulator. This gives the system the ability to emulate true
asynchronous clock domains. The Palladium prefers to have its clocks
internally generated. All external input clocks are sampled by an internal
system clock, which results in synchronous clock domains.
So, which is the better emulator? My manager favored the Palladium because
of its friendlier debugging capabilities and its faster compile time. I
favored the VStation because of its ability to support asynchronous clock
domains and its faster run-time speed. But, ultimately, the decision as to
which emulator we were to use rested with our Financial Controller, who
being a good employee of a Dutch company decided on the cheaper option,
which was the VStation. But that did not mean that the Palladium never
made it into Philips, just not this site.
- Fiona Chua
Philips Semiconductors Southampton, UK
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