( ESNUG 442 Item 11 ) ------------------------------------------- [03/24/05]
Subject: ( ESNUG 441 #2 ) Synopsys Explains its "DFT Compiler MAX" News
> I've read the press release 3 times and I can't tell if this is really
> something new or if it's just Synopsys Marketing serving up warmed over
> DFT Compiler leftovers and calling it new (sort of like repackaging
> DC & PhysOpt & Astro and calling it "Galaxy".)
>
> - John Cooley
> ESNUG/DeepChip.com Holliston, MA
Hi John,
I'm a member of the R&D test automation team at Synopsys working on the
DFT Compiler MAX product. This is in fact new technology. I know. I came
up with it. The following picture is a simplistic view of MAX's "Adaptive
Scan" architecture:
Combinational circuitry on the input and output of the scan chains is used
to match a small scan interface on the chip boundary to a wider scan
interface internal to the design. The picture has a 3 scan chain interface
on the chip boundary delivering test data to 7 scan chains internal to the
design. Thus 9 bits of input stimulus delivers data to 21 scan cells.
Similarly, on the test response side 9 bits of data represents the response
of the test pattern as captured in the 21 scan cells. This is the
reduction in test data volume. Since our architecture allows more internal
scan chains in the design these scan chains are much shorter than those
implemented in a traditional scan architecture. This provides shorter
shift times and hence less test application time.
Multiplexers are used on the input side to prevent encoding steps that do
not work well for scan-ATPG methods. XORs are used on the output to
tolerate unknown values (X’s) with high observability. With a number of
tricks in the design of Adaptive Scan we have been able to achieve our
goal of making the scan testing more efficient.
Adaptive Scan steers a small number of bits from the scan ports with
combinational logic to amplify them to many flip-flops. Up until now high
scan compression (like Mentor's TestKompress) was only achieved with
complicated finite state machines. Combinational logic uses less area
than sequential logic and is easy to implement. Adaptive Scan's
combinational logic can be transparently inserted during scan insertion.
Any DC user can flip a switch and implement this technology. Just add the
following command to your existing DC script:
set_dft_configuration -scan_compression
I hope this helps your readers understand how our scan compression works
without state machines or clock trees.
- Rohit Kapur
Synopsys, Inc. Sunnyvale, CA
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