( ESNUG 442 Item 6 ) -------------------------------------------- [03/24/05]
Subject: ( DAC 04 #40 ) Tiny Accelicon Start-up Just Happy To Be Noticed!
> Accelicon had the most impressive new tool for analog layout transistor
> level floorplaning presented at DAC 2004. The name is Analog Virtual
> Prototyping (AVP) together with the Analog Silicon Implementation (ASI).
> It is an analog solution for automated placement for devices. Imports
> a schematic from Cadence, analyzes the critical path based on Spectre
> or HSPICE simulator results, partitions the design and generates
> automatically a floor plan with real size device.
>
> This tool is much more intuitive then NeoCell or anything else I have
> seen yet. If you are in analog world, it is definitively worth looking
> at Accelicon.
>
> - Dan Clein, author of "CMOS IC Layout"
From: Tim Smith <tsmith=user domain=accelicon-da spot calm>
Hi, John,
We were pleasantly surprised when we saw Dan Clein's review of our Analog
Virtual Prototyping (AVP) tool in your DAC'04 Trip Report (Item 40). The
exposure we received has resulted in 3 serious inquiries from potential
customers interested in evaluating AVP, 38 demoviews from our online demo,
and traffic on our webpage is up 25%. For a small company like us selling
an analog tool, it's a big thing. We don't get offical press coverage.
I'd like to thank you for giving EDA startups like us the opportunity for
early exposure. I believe there is significant value to the user, and to
the vendor, to have new EDA solutions addressed in DeepChip because is
viewed as an objective and credible source. Thanks.
- Tim Smith
Accelicon Technologies Cupertino, CA
Index
Next->Item
|
|
