( ESNUG 442 Item 4 ) -------------------------------------------- [03/24/05]
Subject: ( ESNUG 435 #7 ) A Bunch Of Happy First Encounter Users Chirp Up
> Our current flow consists of Jupiter-XT for floorplanning, PhysOpt for
> placement, Astro to finish up the job, and sign-off with PrimeTime.
> Astro rev is 2003.09-SP2-6. I took two of our biggest chips (0.15 u,
> 6 LM technology) and ran it through the PNA flow and results were
> available within 30 min; compared to our current Simplex flow which
> takes 12 hours to run. The other good thing about Jupiter-XT is it
> requires very minimal input. Since it and Astro share the same Milkyway
> database, iterating to achieve an acceptable PG grid is now much
> simpler. Its IR analysis results also came within 10% of VoltageStorm.
>
> - Manny Macatula
> Conexant Systems, Inc. San Diego, CA
From: Stephane Cesari <stephane.cesari=user domain=st spot calm>
Hi John,
Our designs are CMOS, 90 nm, mixed flat and hierarchical chips.
We use a top-down hierarchical design flow (physical partitioning,
floorplaning, and timing budgeting). This classical design process
is complemented by using a "virtual" flat chip level prototyping
approach in SoC Encounter to validate the feasibility of the design.
Using the block placer, we perform a complete floorplan exploration
placing guides, hard macros and analog blocks. FE allows us to
provide earlier physical information to validate architecture, do
the pad ring assessment, and give the first die size estimation.
Then we perform the partitioning, grouping IPs into sub-systems
(P&R units). For each sub-system, which will be implemented
separately, we must deliver physical constraints coming from the
top level. Amoeba places memories and standard cells into the
partitions (fences). Ports are placed using the automatic pin
assignment (global route based). The power grid is designed using
their power planning tool. (This is the actual physical
floorplaning step.)
Then timing budgeting occurs. Running a virtual IPO on boundary
nets, using the What-If timing mode. This allows you, on-the-fly,
to simulate modifications of black box timing arcs along with
subsequent STA - Exploration before commitment. This reduces the
WNS and we generate SDC's for each P&R unit.
When moving to P&R units implementation, SoC Encounter can provide
valuable information regarding its feasibility using its native
prototyping functions.
After 1 year working with Cadence to stabilize this flow, we can now
say that SoC Encounter allows us to perform floorplaning, prototyping,
partitioning and budgeting in one tool -- sharing the same services
and database.
- Stephane Cesari
STMicroelectronics Grenoble, France
---- ---- ---- ---- ---- ---- ----
From: Hoon Yean Ling <hoon.yean.ling=user domain=philips spot calm>
Hi John,
We taped out our 90 nm testchip successfully using SoC Encounter. Great
support from the Cadence support team. We'll continue to use the
tool in our next project.
- Hoon Yean Ling
Philips Semiconductors Singapore
---- ---- ---- ---- ---- ---- ----
From: Satheesh Kumar Sompalle <ssompalle=user domain=in.ibm spot calm>
Hi John,
In IBM Bangalore we have been using First Encounter for a long time and
are very happy with it. It's good both for floorplanning and
prototying. In my opinion, Synopsys is still lagging in this area.
- Satheesh Kumar Sompalle
IBM Bangalore Bangalore, India
---- ---- ---- ---- ---- ---- ----
From: Don Garrett <dgarrett=user domain=incyte-inc spot calm>
Hi, John,
I have been working in IC physical design for 25 years, everything form
pushing polygons to floorplan, place & route of large SoC designs, writing
support code to building LVS/DRC decks. I began using First Encounter
this year and from what I have experienced it is quite adequate at getting
the job done.
I have no experience with Jupiter-XT, but I have used other floorplanners.
The idea of prototyping is to validate your floorplan early on. If the
prototyping tools correlate with the signoff router/RC extractor, then
you get a good idea of how things will pan out in short order.
I have completed small designs quickly using their Nano Encounter suite;
it can build the floorplan, including the power grid, and validate the
floorplan in relatively few cycles. I look forward to using SoC Encounter.
- Don Garrett
Incyte, Inc. Langhorne, PA
---- ---- ---- ---- ---- ---- ----
From: Amal Reddy <areddy=user domain=amplecomm spot calm>
Hi, John,
This is to let you know that we use FE for our floorplanning.
- Amal Reddy
Ample Communications Fremont, CA
---- ---- ---- ---- ---- ---- ----
From: Prathibha Mohan <mprathib=user domain=in.ibm spot calm>
Hi, John,
I've been working on a COT flow for over a year, using several Cadence
and some Synopsys tools. I've been using First Encounter for place and
route (version 4.1 currently), and haven't had any problems with it.
I've done 5 testcases from 130 nm to 90 nm using this tool, and found
that its not only a prototyper, but a very good floorplanner, too.
- Prathibha Mohan
IBM Bangalore Bangalore, India
---- ---- ---- ---- ---- ---- ----
From: Catherine Xia <catherine.xia=user domain=fmal.fujitsu spot calm>
Hi, John,
I'm PD engineer, and I had used Astro/Apollo & FE for P&R. Now I'm using
First Encounter to partition, floorplan, place, and IPO. It's very
helpful in handling the hierarchy and timing of a design. From the top
level it helps to have a clear and accurate forecast of the design
structure, clock structure, and timing of the total design.
For clocktree generation, I use Celestry ClockWise. It seems to work
well, but its runtime is too long to handle large designs. We use
NanoRoute or Wroute (not embedded) to route, and CeltIC to extract
the RC parameters.
- Catherine Xia
Fujitsu Singapore
Index
Next->Item
|
|
