( ESNUG 441 Item 9 ) -------------------------------------------- [03/09/05]
Subject: ( DAC 04 #42 ) Two Users Add Their Own Zenasis ZenTime Reviews
> Zenasis sells tools that create new cells to speed your critical path in
> a COT flow. They identify groups of cells in your critical path and
> create a single new cell, which may involve reducing the number of logic
> levels, sizing transistors, etc. Their tools interact with Cadabra and
> Calibre to create layouts for the new cluster cell. They claim a 10% to
> 15% speed increase. Their tools work with Synopsys, Cadence and Magma;
> foundries they support include TSMC and UMC.
>
> - John Weiland of Intrinsix Corp.
From: Michio Komoda <komoda.michio=user domain=renesas spot calm>
Hi John,
My group does SOC and MCU designs. We use Zenasis' ZenTime timing
optimization product, which automatically creates new cells to fit
individual designs in order to meet timing. We started to evaluate
Zenasis in 2002, and began to use it on production designs this year.
Our first tape-out using ZenTime is targeted for around September of
this year.
Zenasis helped us to set up ZenTime for use with our designs, including
checking all required data prior to installation. We had no problems,
and with their help finished the set-up in only one day.
ZenTime's continuous sizing feature is useful because it enables
reduction of cell area, and can sometimes improve timing. If the rise
path is critical but the fall path is non-critical, it makes only the
rise path faster. That means capacitance of the input pin is less than
if we were to make both faster. Also, ZenTime's continuous sizing
feature enables low power.
Another ZenTime feature that we liked is the ability to automatically
create a new functional cell implemented at the transistor level, which
reduces the number of levels from the original gate level structure.
Some critical paths have many logic stages, and for these paths, the
sizing is not very effective, due to the dominance of the intrinsic cell
delay. The new functional cells ZenTime creates are especially
effective for this type of critical path because the number of stages
is reduced.
ZenTime's biggest strengths are the ability to introduce a "legacy
style" concept to SoC design with large complex cells and its level of
automation. One drawback is that sometimes it creates many cells,
which can take a long time. We hope that Zenasis will fix this soon.
In the past, when we hit timing problems, we usually used a multi-
threshold technique, which meant adding lower Vth transistors into the
design. That caused more manufacturing steps and thus higher masks costs,
plus increased leakage power. With ZenTime we can use tactical cells to
solve the same the timing problem with the same Vth transistors within
a reasonable time.
We have seen up to 30% speed improvement for designs that were run
through ZenTime. The portion of the design that is touched or changed
is usually less than 10%. However, this percentage will depend on the
amount of timing violations in the design.
We use ZenTime for timing optimizations as an additional step after
layout. ZenTime's interfaces were very complete, and the only additional
work required was to prepare the cell library for the new cells ZenTime
creates. Using ZenTime may not save any design time. However, we expect
it will save mask costs and processing step dramatically, as well as
cycle time.
Though some aspects of ZenTime still need to be improved, we expect
ZenTime to reduce the timing violations considerably without using a
multi-Vth technique. Potentially it will improve timing by 30% delay,
which corresponds to two process generations ahead. So, for example,
even using 150 nm process, in reality with ZenTime we may get 90 nm
process performance.
- Michio Komoda
Renesas Technology Corp. Itami City, Japan
---- ---- ---- ---- ---- ---- ----
From: Seong-Ryeol Kim <sr75.kim=user domain=samsung spot calm>
Hi John,
We build System on Chip and System in Package designs with 90 nm. We have
been using ZenTime from Zenasis for about 8 months now. ZenTimes main
functionality is real-time new cell creation to improve timing. ZenTime
replaces a cluster of cells in a critical path with a new cell that is
optimized at the transistor level.
It took us about a week to set up ZenTime the first time, then only 3
days to set it up for the next design. To set up ZenTime I needed:
- Synopsys .lib
- CDL
- LEF
- Verilog netlist
- Model file
- Timing constraint file (SDC)
- Star-RCXT netlist
ZenTimes biggest strength is automatic cell creation. Its biggest
weaknesses are that it can't read hierarchical design, and it can't
handle asynchronous design.
ZenTime has a continuous sizing feature which is very useful to adjust
timing margin. Occasionally, the design still doesnt have enough timing
margin in spite of using new complex cells. ZenCell increases the
dynamic power of the entire design a little, but this is not a serious
problem for Samsung.
We used ZenTime as a post-synthesis step. Our evaluation of ZenTime has
been focused on designs that don't have any timing margin after logic
synthesis. In fact, we don't yet know how we can apply ZenTime in a
post-layout step.
Our conclusion from our evaluation of ZenTime was that many of the new
cells that ZenTime creates can help in creating a timing margin for the
design. ZenTime's automatic creation of "ZenCells" is especially useful.
The ZenCells aren't characterized by our Samsung method, but we can still
easily estimate the timing margin of optimized designs.
I have run an ARM946 through ZenTime. The runtime was around 18 hours.
The timing improvement was about 14%, and after P&R, the final timing
improvement was about 10%. We used Magma's Blast Fusion place and route,
and the new cells that ZenTime created caused no problems. I think that
if the user can control the Magma options well, P&R will have no problems.
We have now purchased ZenTime and will continue to apply it to various
designs. I am using Zenasis ZenTime for the designs that I am currently
developing though we have not gotten a tapeout yet. So far I have found
that ZenTime is an efficient tool for creating a timing margin, if the
timing margin of the design after Design Compiler is not sufficient.
- Seong-Ryeol Kim
Samsung Hwasung City, Korea
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