( ESNUG 439 Item 7 ) -------------------------------------------- [02/15/05]
Subject: Questions for Ted Vucurevich, CTO of Cadence
Why did Mike Fister really bail on his DesignCon keynote?
---- ---- ---- ---- ---- ---- ----
What is Fister afraid of? He skipped his DC speech.
---- ---- ---- ---- ---- ---- ----
Ted - I was disappointed to see Fister pull a no show at DesignCon. Why
were you covering for him Ted?
---- ---- ---- ---- ---- ---- ----
Ted, Cadence has neither a sign-off timer (your sales force still recommends
using PT-SI for this task), nor a suitable physical verification tool
(Assura is a joke and Dracula died with .25um technology). These are two
critical pieces to be missing, who is your next acquisition to fill these
holes?
---- ---- ---- ---- ---- ---- ----
What happened to the Verplex product line?
---- ---- ---- ---- ---- ---- ----
Q: Why did Cadence spin out SPW to Coware to buy another system
verification tool such as Specman?
---- ---- ---- ---- ---- ---- ----
To Cadence:
Why does Cadence keep changing their CEOs every two to three years?
It seems like Synopsys and Mentor have the same CEO for more than
10years. What's going on inside Cadence? Turf battle?
To Cadence:
From the outside, it seems like Cadence is a company that lives off
of mergers and buying smaller companies. As CTO of Cadence, what
new products does Cadence working on and how do they change the
landscape of EDA industry?
---- ---- ---- ---- ---- ---- ----
You are CTO of a company whose primary claim to fame, in recent years is
based an acquiring technology versus developing it internally...
Verplex, Ambit, Get2Chip, Silicon Perspecitive, Plato, Simplex, Cadmos,
etc. Does Cadence choose this as a strategy, or are these acquisitions
the result of repeated failed internal efforts?
---- ---- ---- ---- ---- ---- ----
Why can't the leadership at Cadence cultivate an environment that leads
to innovative developments to come from within instead of acquiring most
of your new technology?
---- ---- ---- ---- ---- ---- ----
What do Cadence R&D engineers do with their day? Do they spend it
playing foosball tournaments?
---- ---- ---- ---- ---- ---- ----
What went wrong with Ambit (which required you to do a second
acquisition, Get2Chip) versus what went right with Silicon Perspective?
---- ---- ---- ---- ---- ---- ----
Two questions to Ted Vucurevich:
After the last DAC you have announced the next generation tool for timing
convergence "GPS". Is it true that such tool does not exist yet as a
product although almost a year passed since the announcement? What is the
story behind this tool?
Why do you still support two synthesis tools: Get2chip and Ambit? Is it
true that in some internal benchmarks you see better results in Ambit
rather that the new toy from Get2Chip? Who will take over?
---- ---- ---- ---- ---- ---- ----
When would all the Cadences' tools migrate to OA (Open Access)? Two
years have passed since I heard of OA. If Cadence has not migrated their
tools to OA (in core OA database usage), how does Cadence expect EDA
industry to lead porting their tool set to OA. I would expect Cadence
to be the leaders.
---- ---- ---- ---- ---- ---- ----
Primarily for Ted Vucurevich - CTO of Cadence:
There is no mention of System Verilog in any Cadence tutorial or session.
There is a SystemC session. Given the recent Verisity acquisition an
e/SystemC vs. System Verilog war seems imminent. Comment?
---- ---- ---- ---- ---- ---- ----
Let me try one for Ted Vucurevich - CTO of Cadence: who has the better
physical synthesis tool, and why better? why others are worse?
---- ---- ---- ---- ---- ---- ----
3) Vucurevich - Comment on verification using UltraSim and language-based
simulation. Is this market growing? Who do you compete with in this space?
---- ---- ---- ---- ---- ---- ----
When is the next Layout Verification coming out (eTop tool)?
---- ---- ---- ---- ---- ---- ----
Ask Ted when he is going to start pricing commodity features like simple
Composer or VLE as they should be- cheap. Mentor is pricing theirs more
than competitively and Cadence is losing ground. Fast. Time to wake up
and hear the hard disks chattering - they aren't speaking Cadence.
---- ---- ---- ---- ---- ---- ----
With the Cadence/Verisity acquisition will this another RIF to either
company? If so, when will this impact be announced?
---- ---- ---- ---- ---- ---- ----
Will Cadence synthesize E for the Palladium?
---- ---- ---- ---- ---- ---- ----
What was Cadence thinking of when they bought Verisity?
---- ---- ---- ---- ---- ---- ----
What is the time-frame for phasing out 'e'?
---- ---- ---- ---- ---- ---- ----
I would ask Ted why they purchased Verisity.
---- ---- ---- ---- ---- ---- ----
Questions to Cadence:
1) why is spectre so exceptionnaly slow when it comes to simulate
bigger circuits
2) why is there no calibration tool spectre <-> ultrasim/hsim so that in
the
end you know easily the error you have to cope in ultrasim/hsim compared
with the golden simulator spectre
3) the dfII library manager is an exceptionally poor programmed tool:
slow, recursively checks all libs when you only want to open one cell,
or even only want to have an overview of a library
4) mystery cdf: cdf are not updated when you change some pins in your
schematic, so you sometimes end up with a wrong cdl netlist
5) abstract generation tool: abstractGen is a disaster as well as picasso.
I am always tempted to write some skill code just to generate my LEFs,
6) mystery skill: if you want to retrieve something from your dfII database
you have to take a deep breath and spend hours to get skill working
right.
|
|
