( ESNUG 439 Item 5 ) -------------------------------------------- [02/15/05]
Subject: Questions for Antun Domic, Synopsys VP & GM of Implementation
SNPS- Ask him how anyone can possibly believe SNPS that their
implementation flow is fixed and that it offers superior performance to
Magma now... especially since SNPS has been saying that for the last 2
years (which they have to the Wall Street crowd)... They've been crying
wolf for 2 years, so why should we listen now... or better yet- ask him
WHY they cried wolf for the last 2 years when it clearly wasn't true.
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Please ask Antun how many DC customers has he lost to Blast Create and
Cadence Get2chip in the last round of VPA's?
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What's going to happen to Synopsys if Cadence Get2chip destroys your bread
and butter?
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To Antun Domic: When will Synopsys change its business strategy of bundling
Design Complier into "all you can eat" packages with lots of other tools
instead of improving its performance vis-a-vis Magma and Cadence to
maintain its market share?
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To Synopsys:
It seems like formal verification is catching up with smaller
companies like RealIntent Verix and 0-In (now part of Mentor).
Where is Synopsys with their formal product?
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To Antun Domic: Can you explain the basic reason(s) for the revenue
shortfall announced by Synopsys in July 2004, apart from the TBL
changeover (which is hogwash) ?
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One question for Synopsys:
When will they stop waffling and take a clear stand on OpenAccess
and whether or not they really support the bridge with Milkyway.
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I would ask Synopsys at least, or both Synopsys and Cadence, if they
think statistical timing is important. If not, why not?
If so, when are they going to get on the ball? At what process point do
they think it's important to start doing this? (Cobra is targeted at
65nm. IBM uses VAT, even at .13u)
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The latest Astro version (2004.12) is suppose to contain the same placement
engine as Physical Compiler (PhysOpt) and alot of the timing optimizations
(especially xtalk and noise) require a detailed route to be accurate, so is
the need to use PhysOpt going to go away?
If not, do you have any quantitative results showing the benefits gained
from PhysOpt->Astro flow verses just a pure Astro flow?
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Ask Anton why they just don't add the Astro router to PhysOpt?
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I would ask Antun what they are doing to improve quality. Their
competition is quickly surpassing them. Our Synopsys tools are much
less stable compared to the competition. We are starting to get better
results from Get2chip. We are able to process more instances on the
competition.
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What is your opinion on statistical static timing analysis, and when will
you be selling tools that account for the kinds of design variability
that we see in 65nm?
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I would ask Antun if and when Synopsys will ever add a set_ideal_network
to PrimeTime. (This is needed very badly to do timing analysis on
netlists prior to clock tree insertion).
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Q1) Is there a plan to support PSL with System Verilog and/or Vera?
Q2) Will Synopsys make Vera be obsolete once SV is mainstream?
Q3) Is there a plan to support synthesis for VHDL2xxx and beyond?
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How will Synopsys address their lack of superior power analysis
products compared to companies like Apache and Sequence?
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Antun Domic - VP & GM of Implementation, Synopsys
"Why has Synopsys rate of innovation slowed significantly?"
There are not many new products/technology emerging from Synopsys, as it
used to known for (in 86-96 time frame).
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4) Domic - Why is there so much litigation between Synopsys and Magma?
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Antun Domic - VCS 7.2 still doesn't support System Verilog Testbench
(the full 3.1a spec). Will that feature be on its way shortly, or is
Synopsys going to emphasize the VCS-exclusive NTB for the future?
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How many customers are really designing with System Verilog, rather than
just buying it in a package because they think everyone else is doing it?
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What is the status on supporting System Verilog? It seems that everybody
just claims to support it but when you actually try to use it they come
back and say that you have to wait for another release or two. We went
through the same thing with Verilog 2001. I'm sick of this.
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Comment on System Verilog touting many of the features that give Specman
and Vera their value.
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To SNPS -- How much business has Magma take from you last year (assuming
Magma did not exist and everyone else did?)
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What is your opinion on WAN licenses? In past years, we worked on a project
at one location. Nowdays we are working with several different companies
spread all over the world on the same project. Legally we can only run your
compiler at one site.
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Our RTL to GDS implementation flow toolset is all Synopsys. Based on our
recent 130 nm SOC tape-out experiences, your toolset has been found to be
lagging - frequent crashes, long run-times, so-so QOR, poor integration,
shoddy documentation. Your field thinks the fix is to throw more CAE's at
us when the symptoms point clearly to a dysfunctional development
organization. Is this issue properly recognized at the highest levels of
Synopsys? What's being done to fix it? We're not contemplating
alternatives at this point, but our patience is running out.
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Why after all the work for the COSMOS environment you FIRED all the design
team? Why is the tool so expensive (around 125K)? Do they plan to write
another one or just kill this one?
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When will Synopsys have a wide range support for PDK's to support their
plans in compete against Cadence ADE ?
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I would like you to ask Synopsys why the language used to control
synthesis, (timing constraints and such) should not be in the public
domain like any other key deliverable in the design creation process.
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Synopsys is moving tools to the MilkyWay database, this eases transfer of data
betwen DC/PhysOpt/Astro/Jupiter. All well and good. However, the old way of
doing things did have some benefits -- it allowed multiple engineers to work
concurrently. Someone could be generating a new netlist from new RTL in DC,
while someone else is trying to achieve timing closure in PhysOpt, while....
well you get the picture. So, MilkyWay only allows one person access at one
time (I believe) - so has Synopsys just serialized the design process?
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Antun: Are you guys still committing immigration fraud?
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