( ESNUG 435 Item 2 ) -------------------------------------------- [12/08/04]
Subject: Cooley Slapped For No Magma In The Power Part Of The DAC Survey
> HOW ABOUT POWER DESIGNING TOOLS LIKE Sequence PowerTheater? Synopsys
> Power Compiler & PrimePower? Apache SkyHawk? ChipVision Orinoco?
> Atrenta SpyGlass LP? Golden Gate GoPower/IC Plan/PowerRoute/PIE?
From: [ No. 5 on the Island ]
Hi John,
Where is Magma in the power part of your survey?
I saw Magma's low power demo at DAC and have since evaluated version 4.2.
Their low power solution consists of Blast Power, Blast Rail, and Blast
Fusion. The cool thing is that everything that Magma claimed publicly at
DAC, they actually have hard dates for -- a lot of times this doesn't
happen. What I saw in Magma's low power demo that I know works because
I saw in my own eval:
1. Clock Gating. This is required because more than half of the dynamic
power is via the clock tree. You can save dynamic power by gating off
portions of the clock that is not in use.
2. Integrated Signal integrity analysis. At the place and route stage,
Magma's tools understand how signals that route next to each other in
long routes affect each other from a timing standpoint.
3. Multi VT support. They claim to support inserting low VT devices for
least impact on leakage. We want their tool to choose the minimal
number of low VT, lowest leakage devices that still meet timing.
4. Dummy metal insertion to reduce IR drop. To reduce planarization
problems in multilayer process, the fab rule is that for a certain
size area, density must be a specific number. To get this density,
small square or rectangular metals need to be arrayed in open areas
without touching each other or anything else. Magma inserts extra
metal connecting to power rails. In their demo they claimed that
they reduced static 50% activity and IR drop by 30%.
Stuff in the Magma power flow that I know does not work from my eval:
1. Magma deploys Java as little applets that run along with their code.
Three times within 2 weeks I typed ahead too fast for Java to keep up,
which caused a Java memory error and overflow to stacks. We were
running Magma on a very new 2.6 Linux kernel. I could not duplicate
behavior on release 3.0.
2. I also had 3 segmentation faults (signal 11), but think that was
related to having multiple Magma applications up during power
analysis. I was attempting to pull up a schematic view and had not
closed the power analysis tool. On the good side, it was extremely
easy to get back where I was -- it typically takes only 5 minutes.
3. VT CMOS back bias support. I want to see the ability to use and
comprehend the back gate or threshold biasing. They don't have this.
4. Intelligent decoupling cap insertion. As a rule, we fill the white
space with gate capacitors because they have higher capacitance. If
they are strategically inserted where there is a lot of dynamic noise,
then we lower the IR drop as it relates to the dynamic noise. Magma
doesn't have this yet.
5. Incremental power grid generation. Automatic as well as localized
power rail generation. This is for reuse, floor plan modifications
as well as new IP. You draw a rectangle for an area and it generates
the power for that region based on a configuration file. I would
like it if they got this.
What I saw in Magma's low power demo which I don't know if it works or not.
(I haven't yet verified them in my evaluation.)
1. Thermal analysis. They say it helps you understanding where the hot
spots are, as temperature affects leakage.
2. Easy to use dynamic IR drop graph or picture. I have only seen
Magma's static IR drop graphs. I believe that dynamic would be easy
to use, but I have not tested this out. This helps in understanding
power consumption within a clock cycle in time slices.
3. MTCMOS back biasing. Tedious but necessary to reduce leakage.
4. We need support for gated rail at both the block and gate level. We
gate off the channel stack low VT device with a high VT footer to
reduce leakage.
5. Electro Migration-aware placement w/slots. They claim you can insert
"fat" metal power rails up front, and then do your power analysis as
the rails are fully slotted from the beginning. The placement is
aware of the dynamic power. Magma says they place power hungry cells
near power well connected power and smaller ones farther away.
6. Analysis of .lib representation of state dependant leakage. Magma's
tools supposedly recognize that there are particular states that are
lower leakage than others and reports state dependant leakage power.
7. They claim they can do automatic insertion of level shifters across
voltage boundaries. Because we are so power sensitive, we have
9 voltage domains and need a level shifters across those domains,
it would be a tremendous schedule saver to automate the process.
8. Power aware placement. Net length reduction. Magma did a study and
realized that if you take the top 10% of long routes and tuned the
optimizer to shorten all possible without hurting timing, the result
would be a greater than 10% reduction in dynamic power.
9. Retention flop insertion. This means that all the flip flops are on a
separate power supply, which allows all the combinational logic to
power down during stand by, yet maintains the state of exactly where
the processor was prior to going to standby. Naturally, you consume
a lot less leakage current if you only have power to the flip flops
and power down the combinational logic. When you power it back on,
the retention flops supply the previous state to the logic. Neat
stuff if it actually works.
10. IR-Drop induced delay effect. We design extremely low power DSP
cores. Dynamic power analysis is key to understanding the full
effect of full speed events on the power network. In a dynamic
sense, speed is reduced by every small bounce on the power rails.
Magma says these effects must be taken into account if these low
power designs are lowest area and high speed.
11. We are designing in 0.13 um, the knee of the leakage pain. The
generic process leaks more than any wireless application can tolerate
so we design for a higher VT form of the process to reduce leakage.
But for performance, we need to use some lower VT devices -- 90% of
our leakage power comes from these low VT devices. They only make up
a small percentage, but they leak two orders of magnitude more. Magma
says they can handle this.
12. VCD vector and vectorless power analysis. VCD can be a vector file,
while vectorless analysis is algorithmic. Both are in a dynamic
analysis vein. We need to exercise the chip with a given vector to
look at specific instruction-based power issues, plus we need a
vectorless approach to measure a given power plan over another one.
A vectorless approach helps to achieve the right balance between
accuracy and speed.
Overall:
Of the new power features that Magma is offering that Cadence and Synopsys
do not have, what stands out are: the MTCMOS gated rail, incremental power
grid generation, power-aware placement, and EM-aware placement.
The big thing I really liked is that everything is integrated. I can not
stress that too much. In Magma's integrated viewer, there is a schematic
viewer that allows you to probe timing paths or any path of interest by
clicking along the node of the next device. An HSPICE netlist can be
generated of a critical path with Magma extracted parasitics. Sometimes
pictures can help a lot with debug.
They perform signal integrity analysis with Blast Noise as they do place
and route. It is not separate step, so you don't need to generate huge
files, back annotate a netlist and then generate an ECO. Magma says that
you still need a signal integrity tool for sign-off. They claim to work
well with Sequence's Physical Studio, and Sequence confirmed that Magma
users do in fact use them for sign-off.
I have used an evaluation copy of 4.2 and have looked at Magma's static IR
drop analysis for a 42 sq mm transistor chip. We extracted the power
information for the chip's power rails in 12 seconds within Magma's viewing
tool. It is interactive and runs fast. Static current analysis assuming a
50% activity rate ran in only 5 minutes all on an AMD Opteron 64-bit.
We ran the current analysis on the full chip. It runs in only 5 minutes
and highlights real problems in colors that you can see at the top level.
Within Magma, power analysis doesn't look like a separate tool, because it
is fully integrated. You can run an EM analysis looking for current
problems in vias in 7 minutes, and see the same sort of images at the top
level, which you can also zoom in on and check the real layout with the
error over-laid.
Within an hour, I can locate and fix my entire power rail and via issues.
Keep in mind that all of this analysis has been accomplished without ever
leaving the interactive tool. I did not have to export a GDS or Milkyway
database and run STAR.
I rated Magma as the best physical implementation toolset at DAC. I am
still in the process of proving if I can use it. So far it is very
promising. In our evaluation, Magma closed timing in 3 weeks on a very
difficult design, when no one else could.
- [ No. 5 on the Island ]
Editor's Note: There's an online demo of Magma Blast Power at
http://www.deepchip.com/demos/demo0435-02.fhtml -- I would love
to hear what other users have to say about it in ESNUG. - John
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