( ESNUG 434 Item 1 ) -------------------------------------------- [11/18/04]
Subject: ( SNUG 04 #5 ) DC User Now Thinks Of Switching Over To Get2chip
> The DC syn_vV-2003.12-SP1 has a huge bug that we have to go back to
> syn_U-2003.03. However, we did compare the DC syn_vV-2003.12-SP1 and
> Cadence Get2chips. DC ran 8 times faster and had a slightly smaller
> netlist. Synplicity ASIC is too primitive for ASIC design.
>
> - Edmond Tam of Global Locate, Inc.
From: Visshwanth Reddy <vreddy=user domain=chelsio spot calm>
Hi John,
I recently got my hands on Get2Chip. I have used Design Compiler as a
synthesis tool for 3 ASICs over a period of 2 years.
Design Compiler has improved quite a bit in terms of timing, area, and
runtime over the past 2 years. At least for the designs I deal with, the
2003 releases of Design Compiler have been very buggy. Since I ran
into quite a few fatal's, I decided not to use DC 2003.* release for our
most recent chip. The 2004.06 Nighthawk release has been a LOT better in
all respects.
It has been about 2 weeks since I have started using Get2chip, I haven't
as yet explored all its features, but I am very thrilled with the results
I am getting.
My complete design has 6 blocks of similar size (600 k gates each) and
complexity. The total time it takes to go from RTL-to-gates for 1 block
is roughly 7 hours using one Design Compiler license. Total time to go
from RTL-to-gates for my whole design is 40 hours using one Design Compiler
license. Using 2 DC licenses, we can churn it out within 24 hours.
Now using a single license of Get2chip, I am able to build my whole design
(all 6 blocks) in 28 hrs!
A DC vs. Get2chip benchmark for 1 block in my design:
Tool and version Slack (ns) TNS Area Runtime Gates
-------------------- ---------- ----- ------- ---------- -----
DC 2002.05-SP1-E1 -1.088 579.9 2,799 K 7 hrs 45 min 550 K
DC 2004.06 Nighthawk -0.711 506.4 2,731 K 6 hrs 53 min 536 K
Get2chip v04.10-p002_1 -0.327 121.4 2,916 K 4 hrs 22 min 573 K
Library : Artisan 130 nm LV Library for TSMC version 2004q1v1
Clock Period : 3.576 ns
Uncertainty : 0.000 ns
Wire Load Model : None
Machine : Intel Xeon 3.06GHz, 512 KB of Cache, 4 GB of Main Memory
OS : Red Hat Linux release 8.0, Kernel 2.4.18-14bigmem on an i686
Notes:
a.) The area listed out for the block includes only standard
cell area
b.) There are 18 Register Files and 1 SRAM in this block
c.) The design has 29.2 K of flops
d.) I used Design Compiler Ultra and Get2chip Ultra licenses to
compile the block
Get2chip seems to out perform Design Compiler in almost all measurable
fronts. Surprisingly, the timing engine in Design Compiler seems to agree
with Get2chip's timing engine -- at least when I am timing my design with
no_wire_load.
Because of the results I'm seeing here, I'm seriously thinking of switching
over to Get2Chip.
- Visshwanth Reddy
Chelsio Communications Sunnyvale, CA
|
|
