( ESNUG 433 Item 3 ) -------------------------------------------- [10/20/04]

From: Raj Raina <rajesh.raina=user domain=freescale spot calm>
Subject: Designer Asks Designers "How Does Your Chip Do Power-On Reset?"

Hello John,

Historically we've done Power-On Reset for a chip through global Set/Reset
signals that go to every Flip-Flop on the chip that needed to be Reset
(or Set).  This is invariably an asynchronous operation.

Then came Scan.

For chips featuring full-scan, Power-On Reset can be accomplished by pumping
0's through the scan chains for several hundred clock cycles as the reset
pin is asserted.  A Flip-flop that needs to be "Set" instead, has an
inverter placed before the Scan-in and after the Scan-out ports of the
flip-flop.  Indeed several of our chips accomplish reset via scan.  (LSSD
designs use chain flush in order to initialize the FFs)

Today, while most of our chip designs have adopted full-scan technology,
quite a few designs still perform set/reset functions asynchronously using
global signals.

The advantages of Reset-via-Scan are:

  1. Can use scan FFs without Set or Reset ports. Smaller area.
  2. No need for global routing of Set/Reset signals

The drawbacks of Reset-via-Scan are:

  1. EDA tools do not support an automated implementation of Reset-via-Scan
  2. Several hundred cycles are required for chip reset
  3. More complicated to comprehend.

My questions to the ESNUG chip design community are "How does your chip do
Power-On Reset?" and "why do you do it that way?"

    - Raj Raina
      Freescale Semiconductor                    Austin, TX