( ESNUG 431 Item 3 ) --------------------------------------------- [07/14/04]
From: Rick Sedlak <rick_sedlak=user domain=mentor spot calm>
Subject: 5 Ways Users Can Mess Up Their Calibre-xRC Parasitic Extraction
Hi, John,
I do customer support for Calibre-xRC and thought I'd share with you the
top five ways users can derail their Calibre-xRC parasitic extraction
analysis of their chip:
1) "We delay Parasitic Extraction until 3 days before tapeout... or
better yet until after tapeout!"
I get customers calling me personally who clearly don't have a clue
as to how to use Calibre-xRC and it's a week before tapeout! These
people obviously want their chip to fail and I applaud this aplomb!
It takes guts to live this dangerously! Especially when timing,
power and signal integrity have such a great impact on yield.
I'd give LPE (Layout-Parasitic-Extraction) and analysis at least a
month in any schedule I'm on. You need time to dig into the critical
path behavior you're seeing on the chip. Sometimes the clock gets
there before the data. Sometimes that data gets there too early and
is gone by the time the clock arrives. Crosstalk can bite you. I
know users who route their clock right along side their power in
hopes of shielding it from crosstalk. The power rail is one giant
cap. Substrate noise, electromigration on their power nets, via
resistance, are all issues my customers are seeing and it takes much
more than 3 days to fix such headaches.
2) "We nitpic every single parasitic R and C in the net models instead of
reviewing the simulation output for reasonable results."
This is a sure way to get bogged down in the soup of the detail.
3) "We begin parasitic extraction before we have a clean LVS. What
do we need clean LVS for? We just want to get an early look at
the impact of the routing on the design."
Are you going to HSIM, Eldo, Spectre, or PrimeTime with this LPE
netlist?
If your layout is not yet a faithful representation of your
schematic (SOURCE) data, why would you expect that it will give
anything of interest in simulation? Without a clean LVS, your
simulation is just a pipe dream - wishful thinking at best. There
might be parts that work right and there might be parts that don't
work right; you simply don't know!
Also, if your layout is not yet completely hooked-up with routing,
the LPE netlist will have open connections on incomplete nets. Even
if you force a virtual connection, they will not represent the layout
properly relative to the final circuit design. Keep this in mind
when you do LPE analysis.
4) "We add lots and lots and lots of virtual connections in our LVS
runs. We do this to fake out a "clean" LVS. For example, if our
power isn't fully hooked up in our layout, we just go crazy with
virtual connections."
This will hurt because in your extraction netlist, you'll have broken
power nets and many devices simply won't work during simulation.
(Calibre xRC has a workaround for this problem where it will hook up
the virtual connections, but its scary to have it connect up disjoint
pieces that you may or may not have intended. You should be doing
all your own connectivity in your design.) You want a faithful
representation of what your chip will ultimately be when its done.
5) "We didn't take training on the Calibre xRC product. We just
launched into parasitic extraction expecting that we are smart
enough to figure out how to optimally use any tool on the market
in a matter of minutes."
John Hutchins of Legerity, presenting his "Lessons Learned" at the
recent Mentor Graphics User2User conference in Santa Clara, CA
(Apr 19-21, 2004) stated repeatedly:
Take the Training,
Take the Training,
Take the Training !!!!!
I hope these 5 pearls of wisdom help your readers do better extraction.
- Rick Sedlak
Mentor Graphics Wilsonville, OR
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