( ESNUG 431 Item 2 ) --------------------------------------------- [07/14/04]
Subject: ( ESNUG 429 #3 ) 2 Years Ago Get2chips Had 5X Capacity Over DC
> Can you refer me to any published benchmarks between Cadence (Get2chip)
> RTL Compiler vs. Synopsys Design Compiler?
>
> - Neil Horowitz
> TelASIC Communcations El Segundo, CA
From: Srinivas Kukutla <srinivas.kukutla=user domain=procket spot calm>
Hi John,
I wanted to report on Cadence's RTL Compiler (their Get2Chip synthesis
tool). Its been over 2 years since we moved to Get2chips. Moreover we
do not have Synopsys Design Compiler licenses since then.
Our HDL coding has also evolved versus what our DC experience had taught us
to do. We used to hand code two-level logic expressions for critical
control and switching logic to manually flatten it out. With Get2chips we
can get higher performance out of the process by using a "higher-level"
coding style.
Frankly, one reason we were able to quickly adopt this Get2chips in our
production environment was due to the fact that our designs didn't require
a number of features that Get2chips didn't support e.g. hold-time fixing;
group path support; DesignWare components; latch-based design; power
analysis and optimization.
Our design flow is based on the COT model for a 180nm & 130nm CMOS process.
We build our own libraries, RAMs, and use a home-grown floor-planning tool.
We do semi-custom design in the most critical areas of the chip set. We
design large (typically 3-5 M gates), fast chips (400-500 MHz) and timing
closure is the key challenge for us.
We partition based on the backend (the capacity/runtime bottleneck in our
flow). This lets us use the same constraint set for the frontend and the
backend, which simplifies debugging considerably.
Anyway, two years ago we used DC and found its limited capacity required us
to partition our design with typical block size of 300-500K gates. Primary
motivation to try Get2chips was to be able to switch to a top-down instead
of a bottoms-up compile and be able to meet timing because of fewer
optimization boundaries. We also hoped for a faster runtime.
In the beginning, we didn't have confidence in this methodology and actually
ran both the bottoms-up and top-down flows to validate the results. Also,
we had to rely on the Get2Chip team to help us define the top-down .SDC
constraints. Over time we have gained enough confidence in Get2chips and
methodology to only use top-down compile and routinely synthesize 2-3 M gate
blocks. At the time, 2 years ago, this equated to ~5X improvement in
capacity over DC. (300-500K gates vs. 2-3 M gates)
In the front-end flow we write the RTL and simulate with the system models
that are written in C. We use NC-Sim and synthesize at the chip-let level
using a generic recipe.
For a long time Get2chips could not map to complex flops. This was a huge
headache for us because of the double performance and routing penalty. For
one particular block, the Get2chips synthesized area was higher than our
target number and we had to write a Perl script to manually infer the
complex flops.
Get2chips also didn't support scan-chain insertion and we had to create
scripts to manually swap the scan flops. Get2chips used to break our scan
flow due to the uniquification of scanlatch and mem_scan_mux cells. We
did a workaround with the following tcl script:
proc uniqify_scanlatch {} {
set scan_des [find / -null_ok -subdes scanlatch*]
set len [llength $scan_des]
set ret_list {}
set max_index 0
if { $len != {} } {
for { set i 0 } { $i < $len } { incr i } {
lappend ret_list scanlatch$i
#echo $ret_list
}
}
for { set i 0 } { $i < $len } { incr i } {
set old_elem [lindex $scan_des $i]
set new_elem [lindex $ret_list $i]
#set scanlatch_only [regexp {scanlatch$} $old_elem match]
#echo $scanlatch_only
#if { $scanlatch_only == 1 } {
# continue
#}
echo "Renamining $old_elem to $new_elem"
if { [catch {mv $old_elem $new_elem}] } {
for {set j 0 } { $j < $len } { incr j } {
set new_elem [lindex $ret_list $j]
if { [catch {mv $old_elem $new_elem}] } {
continue
} else {
echo "Renamining $old_elem to $new_elem"
break
}
}
}
}
}
proc uniqify_mem_scan_mux {} {
set scan_des [find / -null_ok -subdes mem_scan_mux*]
set len [llength $scan_des]
set ret_list {}
set max_index 0
if { $len != {} } {
for { set i 0 } { $i < $len } { incr i } {
lappend ret_list mem_scan_mux$i
#echo $ret_list
}
}
for { set i 0 } { $i < $len } { incr i } {
set old_elem [lindex $scan_des $i]
set new_elem [lindex $ret_list $i]
#set mem_scan_mux_only [regexp {mem_scan_mux$} $old_elem match]
#echo $mem_scan_mux_only
#if { $mem_scan_mux_only == 1 } {
# continue
#}
echo "Renamining $old_elem to $new_elem"
if { [catch {mv $old_elem $new_elem}] } {
for {set j 0 } { $j < $len } { incr j } {
set new_elem [lindex $ret_list $j]
if { [catch {mv $old_elem $new_elem}] } {
continue
} else {
echo "Renamining $old_elem to $new_elem"
break
}
}
}
}
}
Overall we are dedicated to top-down Get2chips synthesis. It saves lot of
time and meets timing with less iteration. It actually gives a better
insight into which lower level blocks need to be externally synthesized.
Get2chips is easy to use with simple scripting, faster runtimes and better
timing and area post-routing compared to what we saw in DC two years ago.
We have been using Get2chips as our exclusive synthesis tool for two years
and have working silicon back on 7 chips that are in shipped, working
systems. Needless to say, we are happy with the technical capabilities
of the tool and Cadence's customer-support.
- Srinivas Kukutla
Procket Networks, Inc. Milpitas, CA
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