( ESNUG 430 Item 4 ) --------------------------------------------- [06/16/04]
Subject: ( ESNUG 428 #1 ) Verisity Axis Rebuttal To The Palladium Benchmark
> Unfortunately, it turned out that the Axis Verilog simulator wasn't IEEE
> compliant, so we had to modify our Verilog code to do this. It took
> almost 2 months to do this with the Axis AE here most of the time.
>
> Cadence, on the other hand, was quite open that they couldn't do this
> automatically. Actually, being up front about what they had and didn't
> have worked in Cadence's favor during our eval.
From: Ashutosh Varma <ashutosh=user domain=axissystems got calm>
Hi John,
First, the assertion that it took us 2 months to bring-up the design because
we had problems with Verilog compatability is misleading, even if we grant
the poster the assumption that our AE was working on their design
continously for 2 months. Our Verilog solution has been out for almost 5
years and the only things we do not support in our hardware system (RCC)
are gate-level timing and SDF back-annotation (there is limited timing
support available in the software simulator Xsim). We have never claimed
that we support timing sign-off features and always present our system
as a functional acceleration/emulation engine. Sometimes a user's design
depends on delays for correct functional behavior, and it is in those
situations that our AEs may take a little longer to work on a case-by-case
solution which is acceptable to the user. And these solutions are a
one-time investment of effort for bringing up a particular design in our
RCC. Our normal bring-up times are of the order of days and weeks, not
months.
> Axis had a fancier front-end for SA, which shows better in evaluations.
> However, I'm not convinced that it results in more productivity in the
> long run. Experienced users typically shy away from GUIs and fancy
> interfaces once they become familiar and comfortable with a product.
> They typically write scripts to hide all these features, and run in
> batch environments. This is how to get the most performance.
Our GUI front-end is entirely optional and in fact we OEM it from Novas.
Most people use it only for post-processing waveforms and it is typically
not used as a operational front-end into the system.
> When we benchmarked Palladium vs. Axis, Cadence got the in-circuit
> emulation working in less than 2 weeks. Axis could not get it working.
> They tried for many months, and they still don't have a usable system
> to debug code. It was hard to tell whether it was a lack of knowledge
> of the Axis AEs or inherent limitations of the Axis system itself
> that caused this.
Regarding In-Circuit emulation capabilities - as I have said in the
beginning, we have deployed Axis as an emulation system in many new
as well as existing Cadence emulation accounts. Emulation solutions are
highly customized for individual market segments and sometimes even for
particular customers. It is true that particular hardware interfaces
have to be first qualified by us to work with Xtreme emulation systems.
The JTAG system from Metrowerks that has been mentioned was not
qualified, as no other account had requested support for this so far
(and is still the case). We did demonstrate in this benchmark other JTAG
systems including EPI's Majic and ARM's Realview. In addition to this,
we also support Corelis's JTAG system. Our portfolio of ICE interface
support is rapidly increasing, though we started many years after
Cadence/Quickturn in the emulation business.
> Palladium is multi-user. For example, for a 16 million gate box, we
> could fit two 8 Million gate designs simultaneously. We would
> have multiple engineers using Palladium at once, and we wouldn't even
> know that the other engineers were there. Axis keeps promising this
> same feature, but haven't delivered it so far as I can see.
On our multi-user capabilities, I have to restrain myself not to spill
the beans for our Marketing because very soon, you should hear about a
new product supporting this feature. Let me just say that our multi-user
capability will be much more versatile than what is typically present
in other systems.
> With both Palladium and Axis, we could easily look at internal signals.
> When you are not capturing waveforms, Palladium's speed advantage over
> Axis is minor. But once you start capturing waves, Axis slows down by
> a factor of 4, while Palladium maintains its speed. Once you actually
> try to debug something, suddenly Axis is 4 times slower.
On the issue of performance with waveform capture in In-Circuit mode. At
the time we were benchmarking, that was an issue in our system but in
Oct 2003, we came out with 2003.2 software release which addresses this.
With this release, one can expect to see negligible (barely measurable)
difference in In-Circuit performance even when recording the full history.
This can be verified anytime by using 2003.2 or any other later release.
- Ashutosh Varma
Verisity (Axis) Design Inc Sunnyvale, CA
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