( ESNUG 429 Item 2 ) --------------------------------------------- [06/03/04]
Subject: ( ESNUG 424 #1 ) Two More "Nighthawk2" DC Users Chirping Happily
> I wanted to inform you that I am seeing large runtime improvements and
> memory capacity reductions using a special pre-released version of
> Synopsys Design Compiler -- code named Nighthawk2.
>
> - Philip Jackson
> Conexant Systems, Inc. Newport Beach, CA
From: Johnny Zhang <zhozhang=user domain=cisco spot calm>
Hi, John,
After reading Philip Jackson's post in ESNUG 424 #1, we were excited to see
if we could get similar results on our design. We got ourselves a copy of
2004.06 beta to try on a 600 k-instance block from our latest chip. This
block takes 75 hours to compile top-down on DC 2003.12, targeting a 90 nm
high VT library. The job is so huge we need to run on a 64-bit Sun. The
results we got were very exciting: runtime, capacity and area improved
significantly.
We made 2 changes to use the latest and greatest capabilities in the beta.
Nothing major, we were up and running in about an hour.
1. Change from dc_shell to tcl. Easily done with the conversion
program provided in the DC package.
2. Invoked DC in XG mode. XG mode is available on Tcl only.
Amazingly we were able to fit our design on a 32 bit Linux box with the beta
allowing us to take advantage of significantly faster processor speeds. The
runtime and area improvements were just awesome!!!
dc_version: DC 2003.12 Nighthawk DC 2004.06(B)
Machine: 64-bit Sun 32-bit Linux
900 Mhz 2.2 Ghz
Memory: 8 G 2.3 G 3.5X smaller
Compile Time: 75 hrs 24.6 hrs 3X faster
Area: 7403058 5683879 23% smaller
TNS: -5264.14 ns -1770.92 ns 3X lesser
I should mention that we did find one issue that was increasing our TNS by
5X but Synopsys was able to quickly identify and fix the issue and deliver
me a new beta executable. Synopsys seemed to move more quickly after I let
it drop that I would be posting my results on ESNUG. The new executable
resolved the TNS issue and actually improved timing.
Bottom line, this beta shows huge improvements -- 3.5X higher capacity, 23%
smaller area and 3X faster runtime with better timing; very cool!!
- Johnny Zhang
Cisco Systems San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Chandramouli Mahadevan <c-mahadevan=user domain=ti spot calm>
Hi, John,
We tried to see if Nighthawk2 release will make any difference on our
chips. The results are encouraging. I can't provide a lot of details but
suffice to say, that these are multi-million gate designs at 90 nm
running at very high speeds.
Without making substantial changes to our DC scripts, we were able to
improve timing and speed up synthesis by 8-12X with the Nighthawk2 release
compared to the prior version of DC. For the first time, we are also able
synthesize our monster 90 nm chip top-down.
We're eagerly awaiting the official Opteron release of Nighthawk2 to use
its improved performance and capability for sign-off.
- Chandramouli Mahadevan
Texas Instruments Bangalore, India
|
|
